inorder: se: squash after syscalls
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@ -1713,7 +1713,16 @@ InOrderCPU::wakeup()
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void
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void
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InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
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InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
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{
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{
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//@todo: squash behind syscall
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// Syscall must be non-speculative, so squash from last stage
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unsigned squash_stage = NumStages - 1;
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inst->setSquashInfo(squash_stage);
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// Squash In Pipeline Stage
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pipelineStage[squash_stage]->setupSquash(inst, tid);
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// Schedule Squash Through-out Resource Pool
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resPool->scheduleEvent(
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(InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
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scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
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scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri);
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}
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}
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@ -867,7 +867,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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void setFloatSrc(int idx, FloatReg val);
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void setFloatSrc(int idx, FloatReg val);
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void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
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void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
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uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
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TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
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uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
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uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
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/** These Instructions read a integer/float/misc. source register
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/** These Instructions read a integer/float/misc. source register
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