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ARM: Use the new DataOp format to simplify the decoder.

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This commit is contained in:
Gabe Black 2009-07-01 22:11:39 -07:00
parent f409d7819d
commit b8f064c88c
4 changed files with 543 additions and 641 deletions
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2
src/arch/arm/insts/static_inst.cc
View file

@ -388,7 +388,7 @@ ArmStaticInst::printDataInst(std::ostream &os) const
{ {
printMnemonic(os, machInst.sField ? "s" : ""); printMnemonic(os, machInst.sField ? "s" : "");
//XXX It would be nice if the decoder figured this all out for us. //XXX It would be nice if the decoder figured this all out for us.
unsigned opcode = machInst.opcode24_21; unsigned opcode = machInst.opcode;
bool firstOp = true; bool firstOp = true;
// Destination // Destination

5
src/arch/arm/isa/bitfields.isa
View file

@ -34,9 +34,8 @@
// //
// Opcode fields // Opcode fields
def bitfield ENCODING encoding;
def bitfield OPCODE opcode; def bitfield OPCODE opcode;
def bitfield OPCODE_27_25 opcode27_25;
def bitfield OPCODE_24_21 opcode24_21;
def bitfield OPCODE_24_23 opcode24_23; def bitfield OPCODE_24_23 opcode24_23;
def bitfield OPCODE_24 opcode24; def bitfield OPCODE_24 opcode24;
def bitfield OPCODE_23_20 opcode23_20; def bitfield OPCODE_23_20 opcode23_20;
@ -52,7 +51,7 @@ def bitfield OPCODE_19 opcode19;
def bitfield OPCODE_15_12 opcode15_12; def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15; def bitfield OPCODE_15 opcode15;
def bitfield OPCODE_9 opcode9; def bitfield OPCODE_9 opcode9;
def bitfield OPCODE_7_4 opcode7_4; def bitfield MISC_OPCODE miscOpcode;
def bitfield OPCODE_7_5 opcode7_5; def bitfield OPCODE_7_5 opcode7_5;
def bitfield OPCODE_7_6 opcode7_6; def bitfield OPCODE_7_6 opcode7_6;
def bitfield OPCODE_7 opcode7; def bitfield OPCODE_7 opcode7;

566
src/arch/arm/isa/decoder.isa
View file

@ -39,7 +39,7 @@
// //
decode COND_CODE default Unknown::unknown() { decode COND_CODE default Unknown::unknown() {
0xf: decode COND_CODE { 0xf: decode COND_CODE {
0x0: decode OPCODE_27_25 { 0x0: decode OPCODE {
// Just a simple trick to allow us to specify our new uops here // Just a simple trick to allow us to specify our new uops here
0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }}, 0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }},
'IsMicroop'); 'IsMicroop');
@ -56,7 +56,7 @@ decode COND_CODE default Unknown::unknown() {
0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }}, 0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }},
'IsMicroop'); 'IsMicroop');
} }
0x1: decode OPCODE_27_25 { 0x1: decode OPCODE {
0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }}, 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
'IsMicroop'); 'IsMicroop');
0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff; 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
@ -77,158 +77,231 @@ decode COND_CODE default Unknown::unknown() {
} }
default: Unknown::unknown(); // TODO: Ignore other NV space for now default: Unknown::unknown(); // TODO: Ignore other NV space for now
} }
format BasicOp{ default: decode ENCODING {
default: decode OPCODE_27_25 { format DataOp {
0x0: decode OPCODE_4 { 0x0: decode SEVEN_AND_FOUR {
0: decode S_FIELD { 1: decode MISC_OPCODE {
0: decode OPCODE_24_21 { 0x9: decode PREPOST {
format PredIntOp { 0: decode OPCODE {
0x0: and({{ Rd = Rn & Rm_Imm; }}); 0x0: mul({{ uint32_t resTemp;
0x1: eor({{ Rd = Rn ^ Rm_Imm; }}); Rn = resTemp = Rm * Rs; }},
0x2: sub({{ Rd = Rn - Rm_Imm; }}); {{ Cpsr<29:> }},
0x3: rsb({{ Rd = Rm_Imm - Rn; }}); {{ Cpsr<28:> }});
0x4: add({{ Rd = Rn + Rm_Imm; }}); 0x1: mla({{ uint32_t resTemp;
0x5: adc({{ Rd = Rn + Rm_Imm + Cpsr<29:>; }}); Rn = resTemp = Rm * Rs; }},
0x6: sbc({{ Rd = Rn - Rm_Imm + Cpsr<29:> - 1; }}); {{ Cpsr<29:> }},
0x7: rsc({{ Rd = Rm_Imm - Rn + Cpsr<29:> - 1; }}); {{ Cpsr<28:> }});
//0x8:mrs_cpsr -- TODO 0x2: WarnUnimpl::umall();
//0x9:msr_cpsr -- TODO 0x4: umull({{
//0xa:mrs_spsr -- TODO uint64_t resTemp;
//0xb:msr_spsr -- TODO resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
0xc: orr({{ Rd = Rn | Rm_Imm; }}); Rd = (uint32_t)(resTemp & 0xffffffff);
0xd: mov({{ Rd = Rm_Imm; }}); Rn = (uint32_t)(resTemp >> 32);
0xe: bic({{ Rd = Rn & ~Rm_Imm; }}); }}, {{ 1 }}, {{ 1 }});
0xf: mvn({{ Rd = ~Rm_Imm; }}); 0x5: WarnUnimpl::smlal();
0x6: smull({{
int64_t resTemp;
resTemp = ((int64_t)Rm.sw)*((int64_t)Rs.sw);
Rd = (int32_t)(resTemp & 0xffffffff);
Rn = (int32_t)(resTemp >> 32);
}}, {{ 1 }}, {{ 1 }});
0x7: umlal({{
uint64_t resTemp;
resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
Rd = (uint32_t)(resTemp & 0xffffffff);
Rn = (uint32_t)(resTemp >> 32);
}}, {{ 1 }}, {{ 1 }});
}
1: decode PUBWL {
0x10: WarnUnimpl::swp();
0x14: WarnUnimpl::swpb();
0x18: WarnUnimpl::strex();
0x19: WarnUnimpl::ldrex();
} }
} }
1: decode OPCODE_24_21 { 0xb: decode PUBWL {
format PredIntOpCc { format ArmStoreMemory {
0x0: ands({{ 0x0, 0x8: strh_({{ Mem.uh = Rd.uh;
uint32_t resTemp; Rn = Rn + Rm; }},
Rd = resTemp = Rn & Rm_Imm; {{ EA = Rn; }});
}}, 0x4, 0xc: strh_il({{ Mem.uh = Rd.uh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x10, 0x18: strh_p({{ Mem.uh = Rd.uh; }},
{{ EA = Rn + Rm; }});
0x12, 0x1a: strh_pw({{ Mem.uh = Rd.uh;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x14, 0x1c: strh_pil({{ Mem.uh = Rd.uh; }},
{{ EA = Rn + hilo; }});
0x16, 0x1e: strh_piwl({{ Mem.uh = Rd.uh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
}
format ArmLoadMemory {
0x1, 0x9: ldrh_l({{ Rd.uh = Mem.uh;
Rn = Rn + Rm; }},
{{ EA = Rn; }});
0x5, 0xd: ldrh_il({{ Rd.uh = Mem.uh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x11, 0x19: ldrh_pl({{ Rd.uh = Mem.uh; }},
{{ EA = Rn + Rm; }});
0x13, 0x1b: ldrh_pwl({{ Rd.uh = Mem.uh;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x15, 0x1d: ldrh_pil({{ Rd.uh = Mem.uh; }},
{{ EA = Rn + hilo; }});
0x17, 0x1f: ldrh_piwl({{ Rd.uh = Mem.uh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
}
}
format ArmLoadMemory {
0xd: decode PUBWL {
0x1: ldrsb_l({{ Rd = Mem.sb;
Rn = Rn + Rm; }},
{{ EA = Rn; }});
0x5: ldrsb_il({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x9: ldrsb_ul({{ Rd = Mem.sb;
Rn = Rn - Rm; }},
{{ EA = Rn; }});
0xd: ldrsb_uil({{ Rd = Mem.sb;
Rn = Rn - hilo; }},
{{ EA = Rn; }});
0x11: ldrsb_pl({{ Rd = Mem.sb; }},
{{ EA = Rn + Rm; }});
0x13: ldrsb_pwl({{ Rd = Mem.sb;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x15: ldrsb_pil({{ Rd = Mem.sb; }},
{{ EA = Rn + hilo; }});
0x17: ldrsb_piwl({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
0x19: ldrsb_pul({{ Rd = Mem.sb; }},
{{ EA = Rn - Rm; }});
0x1b: ldrsb_puwl({{ Rd = Mem.sb;
Rn = Rn - Rm; }},
{{ EA = Rn - Rm; }});
0x1d: ldrsb_puil({{ Rd = Mem.sb; }},
{{ EA = Rn - hilo; }});
0x1f: ldrsb_puiwl({{ Rd = Mem.sb;
Rn = Rn - hilo; }},
{{ EA = Rn - hilo; }});
}
0xf: decode PUBWL {
0x1: ldrsh_l({{ Rd = Mem.sh;
Rn = Rn + Rm; }},
{{ EA = Rn; }});
0x5: ldrsh_il({{ Rd = Mem.sh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x9: ldrsh_ul({{ Rd = Mem.sh;
Rn = Rn - Rm; }},
{{ EA = Rn; }});
0xd: ldrsh_uil({{ Rd = Mem.sh;
Rn = Rn - hilo; }},
{{ EA = Rn; }});
0x11: ldrsh_pl({{ Rd = Mem.sh; }},
{{ EA = Rn + Rm; }});
0x13: ldrsh_pwl({{ Rd = Mem.sh;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x15: ldrsh_pil({{ Rd = Mem.sh; }},
{{ EA = Rn + hilo; }});
0x17: ldrsh_piwl({{ Rd = Mem.sh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
0x19: ldrsh_pul({{ Rd = Mem.sh; }},
{{ EA = Rn - Rm; }});
0x1b: ldrsh_puwl({{ Rd = Mem.sh;
Rn = Rn - Rm; }},
{{ EA = Rn - Rm; }});
0x1d: ldrsh_puil({{ Rd = Mem.sh; }},
{{ EA = Rn - hilo; }});
0x1f: ldrsh_puiwl({{ Rd = Mem.sh;
Rn = Rn - hilo; }},
{{ EA = Rn - hilo; }});
}
}
}
0: decode IS_MISC {
0: decode OPCODE {
0x0: and({{ uint32_t resTemp;
Rd = resTemp = Rn & op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0x1: eors({{ 0x1: eor({{ uint32_t resTemp;
uint32_t resTemp; Rd = resTemp = Rn ^ op2; }},
Rd = resTemp = Rn ^ Rm_Imm;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0x2: subs({{ 0x2: sub({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = Rn - val2; }},
val2 = Rm_Imm;
Rd = resTemp = Rn - val2;
}},
{{ arm_sub_carry(resTemp, Rn, val2) }}, {{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }}); {{ arm_sub_overflow(resTemp, Rn, val2) }});
0x3: rsbs({{ 0x3: rsb({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = val2 - Rn; }},
val2 = Rm_Imm;
Rd = resTemp = val2 - Rn;
}},
{{ arm_sub_carry(resTemp, val2, Rn) }}, {{ arm_sub_carry(resTemp, val2, Rn) }},
{{ arm_sub_overflow(resTemp, val2, Rn) }}); {{ arm_sub_overflow(resTemp, val2, Rn) }});
0x4: adds({{ 0x4: add({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = Rn + val2; }},
val2 = Rm_Imm;
Rd = resTemp = Rn + val2;
}},
{{ arm_add_carry(resTemp, Rn, val2) }}, {{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }}); {{ arm_add_overflow(resTemp, Rn, val2) }});
0x5: adcs({{ 0x5: adc({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = Rn + val2 + Cpsr<29:>; }},
val2 = Rm_Imm;
Rd = resTemp = Rn + val2 + Cpsr<29:>;
}},
{{ arm_add_carry(resTemp, Rn, val2) }}, {{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }}); {{ arm_add_overflow(resTemp, Rn, val2) }});
0x6: sbcs({{ 0x6: sbc({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = Rn - val2 - !Cpsr<29:>; }},
val2 = Rm_Imm;
Rd = resTemp = Rn - val2 + Cpsr<29:> - 1;
}},
{{ arm_sub_carry(resTemp, Rn, val2) }}, {{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }}); {{ arm_sub_overflow(resTemp, Rn, val2) }});
0x7: rscs({{ 0x7: rsc({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = val2 - Rn - !Cpsr<29:>; }},
val2 = Rm_Imm;
Rd = resTemp = val2 - Rn + Cpsr<29:> - 1;
}},
{{ arm_sub_carry(resTemp, val2, Rn) }}, {{ arm_sub_carry(resTemp, val2, Rn) }},
{{ arm_sub_overflow(resTemp, val2, Rn) }}); {{ arm_sub_overflow(resTemp, val2, Rn) }});
0x8: tst({{ 0x8: tst({{ uint32_t resTemp = Rn & op2; }},
uint32_t resTemp;
resTemp = Rn & Rm_Imm;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0x9: teq({{ 0x9: teq({{ uint32_t resTemp = Rn ^ op2; }},
uint32_t resTemp;
resTemp = Rn ^ Rm_Imm;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0xa: cmp({{ 0xa: cmp({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, resTemp = Rn - val2; }},
val2 = Rm_Imm;
resTemp = Rn - val2;
}},
{{ arm_sub_carry(resTemp, Rn, val2) }}, {{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }}); {{ arm_sub_overflow(resTemp, Rn, val2) }});
0xb: cmn({{ 0xb: cmn({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, resTemp = Rn + val2; }},
val2 = Rm_Imm;
resTemp = Rn + val2;
}},
{{ arm_add_carry(resTemp, Rn, val2) }}, {{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }}); {{ arm_add_overflow(resTemp, Rn, val2) }});
0xc: orrs({{ 0xc: orr({{ uint32_t resTemp, val2 = op2;
uint32_t resTemp, Rd = resTemp = Rn | val2; }},
val2 = Rm_Imm;
Rd = resTemp = Rn | val2;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0xd: movs({{ 0xd: mov({{ uint32_t resTemp;
uint32_t resTemp; Rd = resTemp = op2; }},
Rd = resTemp = Rm_Imm;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0xe: bics({{ 0xe: bic({{ uint32_t resTemp;
uint32_t resTemp; Rd = resTemp = Rn & ~op2; }},
Rd = resTemp = Rn & ~Rm_Imm;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
0xf: mvns({{ 0xf: mvn({{ uint32_t resTemp;
uint32_t resTemp; Rd = resTemp = ~op2; }},
Rd = resTemp = ~Rm_Imm;
}},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }}); {{ Cpsr<28:> }});
} }
1: decode MISC_OPCODE {
0x0: decode OPCODE {
0x8: WarnUnimpl::mrs_cpsr();
0x9: WarnUnimpl::msr_cpsr();
0xa: WarnUnimpl::mrs_spsr();
0xb: WarnUnimpl::msr_spsr();
} }
} 0x1: decode OPCODE {
1: decode OPCODE_7 {
0: decode S_FIELD {
0: decode OPCODE_24_21 {
format PredIntOp {
0x0: and_rs({{ Rd = Rn & Rm_Rs; }});
0x1: eor_rs({{ Rd = Rn ^ Rm_Rs; }});
0x2: sub_rs({{ Rd = Rn - Rm_Rs; }});
0x3: rsb_rs({{ Rd = Rm_Rs - Rn; }});
0x4: add_rs({{ Rd = Rn + Rm_Rs; }});
0x5: adc_rs({{ Rd = Rn + Rm_Rs + Cpsr<29:>; }});
0x6: sbc_rs({{ Rd = Rn - Rm_Rs + Cpsr<29:> - 1; }});
0x7: rsc_rs({{ Rd = Rm_Rs - Rn + Cpsr<29:> - 1; }});
0xc: orr_rs({{ Rd = Rn | Rm_Rs; }});
0xd: mov_rs({{ Rd = Rm_Rs; }});
0xe: bic_rs({{ Rd = Rn & ~Rm_Rs; }});
0xf: mvn_rs({{ Rd = ~Rm_Rs; }});
default: decode OPCODE_7_4 {
0x1: decode OPCODE_24_21 {
0x9: BranchExchange::bx({{ }}); 0x9: BranchExchange::bx({{ }});
0xb: PredOp::clz({{ 0xb: PredOp::clz({{
if (Rm == 0) if (Rm == 0)
@ -245,226 +318,48 @@ decode COND_CODE default Unknown::unknown() {
} }
}}); }});
} }
0x3: decode OPCODE_24_21 { 0x2: decode OPCODE {
0x9: WarnUnimpl::bxj();
}
0x3: decode OPCODE {
0x9: BranchExchange::blx({{ }}, Link); 0x9: BranchExchange::blx({{ }}, Link);
} }
0x5: decode OPCODE {
0x8: WarnUnimpl::qadd();
0x9: WarnUnimpl::qsub();
0xa: WarnUnimpl::qdadd();
0xb: WarnUnimpl::qdsub();
} }
0x8: decode OPCODE {
0x8: WarnUnimpl::smlabb();
0x9: WarnUnimpl::smlalbb();
0xa: WarnUnimpl::smlawb();
0xb: WarnUnimpl::smulbb();
} }
0xa: decode OPCODE {
0x8: WarnUnimpl::smlatb();
0x9: WarnUnimpl::smulwb();
0xa: WarnUnimpl::smlaltb();
0xb: WarnUnimpl::smultb();
} }
1: decode OPCODE_24_21 { 0xc: decode OPCODE {
format PredIntOpCc { 0x8: WarnUnimpl::smlabt();
0x0: ands_rs({{ 0x9: WarnUnimpl::smlawt();
uint32_t resTemp; 0xa: WarnUnimpl::smlalbt();
Rd = resTemp = Rn & Rm_Rs; 0xb: WarnUnimpl::smulbt();
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x1: eors_rs({{
uint32_t resTemp;
Rd = resTemp = Rn ^ Rm_Rs;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x2: subs_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = Rn - val2;
}},
{{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }});
0x3: rsbs_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = val2 - Rn;
}},
{{ arm_sub_carry(resTemp, val2, Rn) }},
{{ arm_sub_overflow(resTemp, val2, Rn) }});
0x4: adds_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = Rn + val2;
}},
{{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }});
0x5: adcs_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = Rn + val2 + Cpsr<29:>;
}},
{{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }});
0x6: sbcs_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = Rn - val2 + Cpsr<29:> - 1;
}},
{{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }});
0x7: rscs_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = val2 - Rn + Cpsr<29:> - 1;
}},
{{ arm_sub_carry(resTemp, val2, Rn) }},
{{ arm_sub_overflow(resTemp, val2, Rn) }});
0x8: tst_rs({{
uint32_t resTemp;
resTemp = Rn & Rm_Rs;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x9: teq_rs({{
uint32_t resTemp;
resTemp = Rn ^ Rm_Rs;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xa: cmp_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
resTemp = Rn - val2;
}},
{{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }});
0xb: cmn_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
resTemp = Rn + val2;
}},
{{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }});
0xc: orrs_rs({{
uint32_t resTemp,
val2 = Rm_Rs;
Rd = resTemp = Rn | val2;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xd: movs_rs({{
uint32_t resTemp;
Rd = resTemp = Rm_Rs;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xe: bics_rs({{
uint32_t resTemp;
Rd = resTemp = Rn & ~Rm_Rs;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xf: mvns_rs({{
uint32_t resTemp;
Rd = resTemp = ~Rm_Rs;
}},
{{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
} }
} 0xe: decode OPCODE {
} 0x8: WarnUnimpl::smlatt();
1: decode OPCODE_6_5 { 0x9: WarnUnimpl::smulwt();
0x0: decode OPCODE_24 { 0xa: WarnUnimpl::smlaltt();
0: decode LUAS { 0xb: WarnUnimpl::smultt();
format PredIntOp {
0x0: mul({{ Rn = Rm * Rs; }});
0x1: PredIntOpCc::muls({{
uint32_t resTemp;
Rn = resTemp = Rm * Rs;
}},
{{ Cpsr<29:> }},
{{ Cpsr<28:> }});
0x2: mla_a({{ Rn = Rm * Rs + Rd; }});
0x8: umull_l({{
uint64_t resTemp;
resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
Rd = (uint32_t)(resTemp & 0xffffffff);
Rn = (uint32_t)(resTemp >> 32);
}});
0xa: umlal_lu({{
uint64_t resTemp;
resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
Rd = (uint32_t)(resTemp & 0xffffffff);
Rn = (uint32_t)(resTemp >> 32);
}});
0xc: smull_lu({{
int64_t resTemp;
resTemp = ((int64_t)Rm.sw)*((int64_t)Rs.sw);
Rd = (int32_t)(resTemp & 0xffffffff);
Rn = (int32_t)(resTemp >> 32);
}});
}
}
}
0x1: decode PUIWL {
0x01,0x09: ArmLoadMemory::ldrh_l({{ Rd.uh = Mem.uh;
Rn = Rn + Rm; }},
{{ EA = Rn; }});
0x04,0x0c: ArmStoreMemory::strh_i({{ Mem.uh = Rd.uh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x05,0x0d: ArmLoadMemory::ldrh_il({{ Rd.uh = Mem.uh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x10,0x18: ArmStoreMemory::strh_p({{ Mem.uh = Rd.uh; }},
{{ EA = Rn + Rm; }});
0x11,0x19: ArmLoadMemory::ldrh_pl({{ Rd.uh = Mem.uh; }},
{{ EA = Rn + Rm; }});
0x12,0x1a: ArmStoreMemory::strh_pw({{ Mem.uh = Rd.uh;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x13,0x1b: ArmLoadMemory::ldrh_pwl({{ Rd.uh = Mem.uh;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x14,0x1c: ArmStoreMemory::strh_pi({{ Mem.uh = Rd.uh; }},
{{ EA = Rn + hilo; }});
0x15,0x1d: ArmLoadMemory::ldrh_pil({{ Rd.uh = Mem.uh; }},
{{ EA = Rn + hilo; }});
0x16,0x1e: ArmStoreMemory::strh_piw({{ Mem.uh = Rd.uh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
0x17,0x1f: ArmLoadMemory::ldrh_piwl({{ Rd.uh = Mem.uh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
}
0x2: decode PUIWL {
format ArmLoadMemory {
0x05,0x0d: ldrsb_il({{ Rd.sb = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x11,0x19: ldrsb_pl({{ Rd.sb = Mem.sb; }},
{{ EA = Rn + Rm; }});
0x13,0x1b: ldrsb_pwl({{ Rd.sb = Mem.sb;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x15,0x1d: ldrsb_pil({{ Rd.sb = Mem.sb; }},
{{ EA = Rn + hilo; }});
0x17,0x1f: ldrsb_piwl({{ Rd.sb = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
}
}
0x3: decode PUIWL {
format ArmLoadMemory {
0x05,0x0d: ldrsh_il({{ Rd.sh = Mem.sh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x11,0x19: ldrsh_pl({{ Rd.sh = Mem.sh; }},
{{ EA = Rn + Rm; }});
0x13,0x1b: ldrsh_pwl({{ Rd.sh = Mem.sh;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
0x15,0x1d: ldrsh_pil({{ Rd.sh = Mem.sh; }},
{{ EA = Rn + hilo; }});
0x17,0x1f: ldrsh_piwl({{ Rd.sh = Mem.sh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
} }
} }
} }
} }
} 0x1: decode IS_MISC {
0x1: decode S_FIELD { 0: decode S_FIELD {
0: decode OPCODE_24_21 { 0: decode OPCODE {
format PredImmOp { format PredImmOp {
0x0: andi({{ Rd = Rn & rotated_imm; }}); 0x0: andi({{ Rd = Rn & rotated_imm; }});
0x1: eori({{ Rd = Rn ^ rotated_imm; }}); 0x1: eori({{ Rd = Rn ^ rotated_imm; }});
@ -484,7 +379,7 @@ decode COND_CODE default Unknown::unknown() {
} }
} }
} }
1: decode OPCODE_24_21 { 1: decode OPCODE {
format PredImmOpCc { format PredImmOpCc {
0x0: andsi({{ 0x0: andsi({{
uint32_t resTemp; uint32_t resTemp;
@ -585,6 +480,15 @@ decode COND_CODE default Unknown::unknown() {
} }
} }
} }
1: decode OPCODE {
// The following two instructions aren't supposed to be defined
0x8: WarnUnimpl::undefined_instruction();
0x9: WarnUnimpl::undefined_instruction();
0xa: WarnUnimpl::mrs_i_cpsr();
0xb: WarnUnimpl::mrs_i_spsr();
}
}
0x2: decode PUBWL { 0x2: decode PUBWL {
// CAREFUL: // CAREFUL:
// Can always do EA + disp, since we negate disp using the UP flag // Can always do EA + disp, since we negate disp using the UP flag
@ -846,7 +750,7 @@ decode COND_CODE default Unknown::unknown() {
}}); }});
} }
} }
} }
} }
} }

7
src/arch/arm/types.hh
View file

@ -44,9 +44,8 @@ namespace ArmISA
Bitfield<32> isMisc; Bitfield<32> isMisc;
// All the different types of opcode fields. // All the different types of opcode fields.
Bitfield<27, 25> opcode; Bitfield<27, 25> encoding;
Bitfield<27, 25> opcode27_25; Bitfield<24, 21> opcode;
Bitfield<24, 21> opcode24_21;
Bitfield<24, 23> opcode24_23; Bitfield<24, 23> opcode24_23;
Bitfield<24> opcode24; Bitfield<24> opcode24;
Bitfield<23, 20> opcode23_20; Bitfield<23, 20> opcode23_20;
@ -62,7 +61,7 @@ namespace ArmISA
Bitfield<15, 12> opcode15_12; Bitfield<15, 12> opcode15_12;
Bitfield<15> opcode15; Bitfield<15> opcode15;
Bitfield<9> opcode9; Bitfield<9> opcode9;
Bitfield<7, 4> opcode7_4; Bitfield<7, 4> miscOpcode;
Bitfield<7, 5> opcode7_5; Bitfield<7, 5> opcode7_5;
Bitfield<7, 6> opcode7_6; Bitfield<7, 6> opcode7_6;
Bitfield<7> opcode7; Bitfield<7> opcode7;