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ruby: adds set and way indices to AbstractCacheEntry

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This commit is contained in:
Nilay Vaish 2015-08-14 19:28:43 -05:00
parent a6f3f38f2c
commit b815221718
2 changed files with 19 additions and 4 deletions
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19
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
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@ -62,9 +62,22 @@ class AbstractCacheEntry : public AbstractEntry
void clearLocked(); void clearLocked();
bool isLocked(int context) const; bool isLocked(int context) const;
Addr m_Address; // Address of this block, required by CacheMemory void setSetIndex(uint32_t s) { m_set_index = s; }
int m_locked; // Holds info whether the address is locked, uint32_t getSetIndex() const { return m_set_index; }
// required for implementing LL/SC
void setWayIndex(uint32_t s) { m_way_index = s; }
uint32_t getWayIndex() const { return m_way_index; }
// Address of this block, required by CacheMemory
Addr m_Address;
// Holds info whether the address is locked.
// Required for implementing LL/SC operations.
int m_locked;
private:
// Set and way coordinates of the entry within the cache memory object.
uint32_t m_set_index;
uint32_t m_way_index;
}; };
inline std::ostream& inline std::ostream&

4
src/mem/ruby/structures/CacheMemory.cc
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@ -251,7 +251,7 @@ CacheMemory::cacheAvail(Addr address) const
} }
AbstractCacheEntry* AbstractCacheEntry*
CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch) CacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch)
{ {
assert(address == makeLineAddress(address)); assert(address == makeLineAddress(address));
assert(!isTagPresent(address)); assert(!isTagPresent(address));
@ -270,6 +270,8 @@ CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch)
address); address);
set[i]->m_locked = -1; set[i]->m_locked = -1;
m_tag_index[address] = i; m_tag_index[address] = i;
entry->setSetIndex(cacheSet);
entry->setWayIndex(i);
if (touch) { if (touch) {
m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); m_replacementPolicy_ptr->touch(cacheSet, i, curTick());