Mem: Eliminate the NO_FAULT request flag.
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8 changed files with 26 additions and 10 deletions
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@ -144,7 +144,7 @@ DtbFault::invoke(ThreadContext *tc)
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// read, like the EV5). The EV6 approach is cleaner and seems to
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// work with EV5 PAL code, but not the other way around.
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if (!tc->misspeculating() &&
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reqFlags.noneSet(Request::VPTE|Request::NO_FAULT)) {
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reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
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// set VA register with faulting address
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tc->setMiscRegNoEffect(IPR_VA, vaddr);
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@ -627,7 +627,7 @@ decode OPCODE default Unknown::unknown() {
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format MiscPrefetch {
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0xf800: wh64({{ EA = Rb & ~ULL(63); }},
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{{ xc->writeHint(EA, 64, memAccessFlags); }},
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mem_flags = NO_FAULT,
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mem_flags = PREFETCH,
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inst_flags = [IsMemRef, IsDataPrefetch,
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IsStore, MemWriteOp]);
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}
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@ -548,7 +548,7 @@ def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
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pf_flags = makeList(pf_flags)
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inst_flags = makeList(inst_flags)
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pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
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pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
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pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
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'IsDataPrefetch', 'MemReadOp']
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@ -619,7 +619,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
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def format Prefetch(ea_code = {{ EA = Rs + disp; }},
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mem_flags = [], pf_flags = [], inst_flags = []) {{
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pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
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pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
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pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
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'IsDataPrefetch', 'MemReadOp']
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@ -326,7 +326,7 @@ CheckerCPU::checkFlags(Request *req)
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{
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// Remove any dynamic flags that don't have to do with the request itself.
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unsigned flags = unverifiedReq->getFlags();
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unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
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unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | PREFETCH;
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flags = flags & (mask);
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if (flags == req->getFlags()) {
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return false;
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@ -353,8 +353,14 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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recordEvent("Uncached Read");
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//If there's a fault, return it
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if (fault != NoFault)
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if (fault != NoFault) {
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if (req->isPrefetch()) {
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return NoFault;
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} else {
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return fault;
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}
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}
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//If we don't need to access a second cache line, stop now.
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if (secondAddr <= addr)
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{
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@ -531,8 +537,12 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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assert(locked);
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locked = false;
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}
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if (fault != NoFault && req->isPrefetch()) {
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return NoFault;
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} else {
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return fault;
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}
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}
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/*
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* Set up for accessing the second cache line.
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@ -273,6 +273,8 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
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{
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_status = Running;
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if (fault != NoFault) {
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if (req->isPrefetch())
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fault = NoFault;
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delete data;
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delete req;
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@ -315,6 +317,10 @@ TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
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{
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_status = Running;
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if (fault1 != NoFault || fault2 != NoFault) {
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if (req1->isPrefetch())
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fault1 = NoFault;
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if (req2->isPrefetch())
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fault2 = NoFault;
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delete data;
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delete req1;
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delete req2;
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@ -360,6 +366,8 @@ TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
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void
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TimingSimpleCPU::translationFault(Fault fault)
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{
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// fault may be NoFault in cases where a fault is suppressed,
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// for instance prefetches.
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numCycles += tickToCycles(curTick - previousTick);
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previousTick = curTick;
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@ -72,8 +72,6 @@ class Request : public FastAlloc
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/** This request is to a memory mapped register. */
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static const FlagsType MMAPED_IPR = 0x00002000;
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/** The request should not cause a page fault. */
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static const FlagsType NO_FAULT = 0x00010000;
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/** The request should ignore unaligned access faults */
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static const FlagsType NO_ALIGN_FAULT = 0x00020000;
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/** The request should ignore unaligned access faults */
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