config: separate function for instantiating a memory controller

This patch moves code for instantiating a single memory controller from
the function config_mem() to a separate function.  This is being done
so that memory controllers can be instantiated without assuming that
they will be attached to the system in a particular fashion.

configs/common/MemConfig.py

@@ -126,35 +126,18 @@ for alias, target in _mem_aliases_all:
         # Normal alias
         _mem_aliases[alias] = target
 
-def config_mem(options, system):
+def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size):
     """
-    Create the memory controllers based on the options and attach them.
-
-    If requested, we make a multi-channel configuration of the
-    selected memory controller class by creating multiple instances of
-    the specific class. The individual controllers have their
-    parameters set such that the address range is interleaved between
-    them.
+    Helper function for creating a single memoy controller from the given
+    options.  This function is invoked multiple times in config_mem function
+    to create an array of controllers.
     """
 
-    nbr_mem_ctrls = options.mem_channels
     import math
-    from m5.util import fatal
-    intlv_bits = int(math.log(nbr_mem_ctrls, 2))
-    if 2 ** intlv_bits != nbr_mem_ctrls:
-        fatal("Number of memory channels must be a power of 2")
-    cls = get(options.mem_type)
-    mem_ctrls = []
-
     # The default behaviour is to interleave on cache line granularity
-    cache_line_bit = int(math.log(system.cache_line_size.value, 2)) - 1
+    cache_line_bit = int(math.log(cache_line_size, 2)) - 1
     intlv_low_bit = cache_line_bit
 
-    # For every range (most systems will only have one), create an
-    # array of controllers and set their parameters to match their
-    # address mapping in the case of a DRAM
-    for r in system.mem_ranges:
-        for i in xrange(nbr_mem_ctrls):
     # Create an instance so we can figure out the address
     # mapping and row-buffer size
     ctrl = cls()
@@ -185,7 +168,37 @@ def config_mem(options, system):
                                           intlv_low_bit + intlv_bits,
                                       intlvBits = intlv_bits,
                                       intlvMatch = i)
-            mem_ctrls.append(ctrl)
+    return ctrl
+
+def config_mem(options, system):
+    """
+    Create the memory controllers based on the options and attach them.
+
+    If requested, we make a multi-channel configuration of the
+    selected memory controller class by creating multiple instances of
+    the specific class. The individual controllers have their
+    parameters set such that the address range is interleaved between
+    them.
+    """
+
+    nbr_mem_ctrls = options.mem_channels
+    import math
+    from m5.util import fatal
+    intlv_bits = int(math.log(nbr_mem_ctrls, 2))
+    if 2 ** intlv_bits != nbr_mem_ctrls:
+        fatal("Number of memory channels must be a power of 2")
+
+    cls = get(options.mem_type)
+    mem_ctrls = []
+
+    # For every range (most systems will only have one), create an
+    # array of controllers and set their parameters to match their
+    # address mapping in the case of a DRAM
+    for r in system.mem_ranges:
+        for i in xrange(nbr_mem_ctrls):
+            mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
+                                             intlv_bits,
+                                             system.cache_line_size.value))
 
     system.mem_ctrls = mem_ctrls