config: separate function for instantiating a memory controller
This patch moves code for instantiating a single memory controller from the function config_mem() to a separate function. This is being done so that memory controllers can be instantiated without assuming that they will be attached to the system in a particular fashion.
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1 changed files with 48 additions and 35 deletions
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@ -126,35 +126,18 @@ for alias, target in _mem_aliases_all:
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# Normal alias
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# Normal alias
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_mem_aliases[alias] = target
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_mem_aliases[alias] = target
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def config_mem(options, system):
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def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size):
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"""
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"""
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Create the memory controllers based on the options and attach them.
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Helper function for creating a single memoy controller from the given
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options. This function is invoked multiple times in config_mem function
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If requested, we make a multi-channel configuration of the
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to create an array of controllers.
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selected memory controller class by creating multiple instances of
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the specific class. The individual controllers have their
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parameters set such that the address range is interleaved between
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them.
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"""
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"""
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nbr_mem_ctrls = options.mem_channels
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import math
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import math
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from m5.util import fatal
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intlv_bits = int(math.log(nbr_mem_ctrls, 2))
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if 2 ** intlv_bits != nbr_mem_ctrls:
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fatal("Number of memory channels must be a power of 2")
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cls = get(options.mem_type)
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mem_ctrls = []
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# The default behaviour is to interleave on cache line granularity
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# The default behaviour is to interleave on cache line granularity
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cache_line_bit = int(math.log(system.cache_line_size.value, 2)) - 1
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cache_line_bit = int(math.log(cache_line_size, 2)) - 1
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intlv_low_bit = cache_line_bit
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intlv_low_bit = cache_line_bit
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# For every range (most systems will only have one), create an
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# array of controllers and set their parameters to match their
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# address mapping in the case of a DRAM
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for r in system.mem_ranges:
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for i in xrange(nbr_mem_ctrls):
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# Create an instance so we can figure out the address
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# Create an instance so we can figure out the address
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# mapping and row-buffer size
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# mapping and row-buffer size
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ctrl = cls()
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ctrl = cls()
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@ -185,7 +168,37 @@ def config_mem(options, system):
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intlv_low_bit + intlv_bits,
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intlv_low_bit + intlv_bits,
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intlvBits = intlv_bits,
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intlvBits = intlv_bits,
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intlvMatch = i)
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intlvMatch = i)
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mem_ctrls.append(ctrl)
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return ctrl
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def config_mem(options, system):
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"""
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Create the memory controllers based on the options and attach them.
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If requested, we make a multi-channel configuration of the
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selected memory controller class by creating multiple instances of
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the specific class. The individual controllers have their
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parameters set such that the address range is interleaved between
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them.
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"""
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nbr_mem_ctrls = options.mem_channels
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import math
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from m5.util import fatal
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intlv_bits = int(math.log(nbr_mem_ctrls, 2))
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if 2 ** intlv_bits != nbr_mem_ctrls:
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fatal("Number of memory channels must be a power of 2")
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cls = get(options.mem_type)
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mem_ctrls = []
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# For every range (most systems will only have one), create an
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# array of controllers and set their parameters to match their
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# address mapping in the case of a DRAM
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for r in system.mem_ranges:
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for i in xrange(nbr_mem_ctrls):
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mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
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intlv_bits,
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system.cache_line_size.value))
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system.mem_ctrls = mem_ctrls
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system.mem_ctrls = mem_ctrls
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