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O3CPU: Fix thread writeback logic.

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Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
This commit is contained in:
Kevin Lim 2008-09-26 07:44:07 -07:00
parent 712a8ee700
commit b784903207
3 changed files with 13 additions and 13 deletions
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8
src/cpu/o3/commit_impl.hh
View file

@ -814,7 +814,7 @@ DefaultCommit<Impl>::commit()
// @todo: Make this handle multi-cycle communication between // @todo: Make this handle multi-cycle communication between
// commit and IEW. // commit and IEW.
if (checkEmptyROB[tid] && rob->isEmpty(tid) && if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
!iewStage->hasStoresToWB() && !committedStores[tid]) { !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
checkEmptyROB[tid] = false; checkEmptyROB[tid] = false;
toIEW->commitInfo[tid].usedROB = true; toIEW->commitInfo[tid].usedROB = true;
toIEW->commitInfo[tid].emptyROB = true; toIEW->commitInfo[tid].emptyROB = true;
@ -968,7 +968,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
"instruction [sn:%lli] at the head of the ROB, PC %#x.\n", "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
head_inst->seqNum, head_inst->readPC()); head_inst->seqNum, head_inst->readPC());
if (inst_num > 0 || iewStage->hasStoresToWB()) { if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
DPRINTF(Commit, "Waiting for all stores to writeback.\n"); DPRINTF(Commit, "Waiting for all stores to writeback.\n");
return false; return false;
} }
@ -983,7 +983,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
return false; return false;
} else if (head_inst->isLoad()) { } else if (head_inst->isLoad()) {
if (inst_num > 0 || iewStage->hasStoresToWB()) { if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
DPRINTF(Commit, "Waiting for all stores to writeback.\n"); DPRINTF(Commit, "Waiting for all stores to writeback.\n");
return false; return false;
} }
@ -1038,7 +1038,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
head_inst->seqNum, head_inst->readPC()); head_inst->seqNum, head_inst->readPC());
if (iewStage->hasStoresToWB() || inst_num > 0) { if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
return false; return false;
} }

3
src/cpu/o3/iew.hh
View file

@ -208,6 +208,9 @@ class DefaultIEW
/** Returns if the LSQ has any stores to writeback. */ /** Returns if the LSQ has any stores to writeback. */
bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
/** Returns if the LSQ has any stores to writeback. */
bool hasStoresToWB(unsigned tid) { return ldstQueue.hasStoresToWB(tid); }
void incrWb(InstSeqNum &sn) void incrWb(InstSeqNum &sn)
{ {
if (++wbOutstanding == wbMax) if (++wbOutstanding == wbMax)

15
src/cpu/o3/lsq_impl.hh
View file

@ -584,17 +584,14 @@ LSQ<Impl>::hasStoresToWB()
std::list<unsigned>::iterator threads = activeThreads->begin(); std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end(); std::list<unsigned>::iterator end = activeThreads->end();
if (threads == end)
return false;
while (threads != end) { while (threads != end) {
unsigned tid = *threads++; unsigned tid = *threads++;
if (!hasStoresToWB(tid)) if (hasStoresToWB(tid))
return false; return true;
} }
return true; return false;
} }
template<class Impl> template<class Impl>
@ -607,11 +604,11 @@ LSQ<Impl>::willWB()
while (threads != end) { while (threads != end) {
unsigned tid = *threads++; unsigned tid = *threads++;
if (!willWB(tid)) if (willWB(tid))
return false; return true;
} }
return true; return false;
} }
template<class Impl> template<class Impl>