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arm: Fix timing wakeup with LLSC

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This commit is contained in:
Ali Saidi 2014-11-12 09:05:22 -05:00
parent 7d05895120
commit b6f32253dd
1 changed files with 6 additions and 6 deletions
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12
src/cpu/simple/timing.cc
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@ -243,6 +243,12 @@ bool
TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
{
RequestPtr req = pkt->req;
// We're about the issues a locked load, so tell the monitor
// to start caring about this address
if (pkt->isRead() && pkt->req->isLLSC()) {
TheISA::handleLockedRead(thread, pkt->req);
}
if (req->isMmappedIpr()) {
Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, clockEdge(delay));
@ -792,12 +798,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
traceData = NULL;
}
// the locked flag may be cleared on the response packet, so check
// pkt->req and not pkt to see if it was a load-locked
if (pkt->isRead() && pkt->req->isLLSC()) {
TheISA::handleLockedRead(thread, pkt->req);
}
delete pkt->req;
delete pkt;