diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc
index 5e08b069d..87a89cc4f 100644
--- a/src/arch/arm/insts/branch.cc
+++ b/src/arch/arm/insts/branch.cc
@@ -32,54 +32,4 @@
 
 namespace ArmISA
 {
-Addr
-Branch::branchTarget(Addr branchPC) const
-{
-    return branchPC + 8 + disp;
-}
-
-const std::string &
-PCDependentDisassembly::disassemble(Addr pc,
-                                    const SymbolTable *symtab) const
-{
-    if (!cachedDisassembly ||
-        pc != cachedPC || symtab != cachedSymtab)
-    {
-        if (cachedDisassembly)
-            delete cachedDisassembly;
-
-        cachedDisassembly =
-            new std::string(generateDisassembly(pc, symtab));
-        cachedPC = pc;
-        cachedSymtab = symtab;
-    }
-
-    return *cachedDisassembly;
-}
-
-std::string
-Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-    std::stringstream ss;
-
-    printMnemonic(ss);
-    ss << "\t";
-
-    Addr target = pc + 8 + disp;
-    ccprintf(ss, "%#x", target);
-    printMemSymbol(ss, symtab, " <", target, ">");
-
-    return ss.str();
-}
-
-std::string
-BranchExchange::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-    std::stringstream ss;
-    printMnemonic(ss);
-    if (_numSrcRegs > 0) {
-        printReg(ss, _srcRegIdx[0]);
-    }
-    return ss.str();
-}
 }
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index 185d34bab..fbdd10d68 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -46,36 +46,6 @@
 
 namespace ArmISA
 {
-/**
- * Base class for instructions whose disassembly is not purely a
- * function of the machine instruction (i.e., it depends on the
- * PC).  This class overrides the disassemble() method to check
- * the PC and symbol table values before re-using a cached
- * disassembly string.  This is necessary for branches and jumps,
- * where the disassembly string includes the target address (which
- * may depend on the PC and/or symbol table).
- */
-class PCDependentDisassembly : public PredOp
-{
-  protected:
-    /// Cached program counter from last disassembly
-    mutable Addr cachedPC;
-
-    /// Cached symbol table pointer from last disassembly
-    mutable const SymbolTable *cachedSymtab;
-
-    /// Constructor
-    PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
-                           OpClass __opClass)
-        : PredOp(mnem, _machInst, __opClass),
-          cachedPC(0), cachedSymtab(0)
-    {
-    }
-
-    const std::string &
-    disassemble(Addr pc, const SymbolTable *symtab) const;
-};
-
 // Branch to a target computed with an immediate
 class BranchImm : public PredOp
 {
@@ -160,50 +130,6 @@ class BranchImmReg : public PredOp
     {}
 };
 
-/**
- * Base class for branches (PC-relative control transfers),
- * conditional or unconditional.
- */
-class Branch : public PCDependentDisassembly
-{
-  protected:
-    /// target address (signed) Displacement .
-    int32_t disp;
-
-    /// Constructor.
-    Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-        : PCDependentDisassembly(mnem, _machInst, __opClass),
-          disp(machInst.offset << 2)
-    {
-        //If Bit 26 is 1 then Sign Extend
-        if ( (disp & 0x02000000) > 0  ) {
-            disp |=  0xFC000000;
-        }
-    }
-
-    Addr branchTarget(Addr branchPC) const;
-
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
-/**
- * Base class for branch and exchange instructions on the ARM
- */
-class BranchExchange : public PredOp
-{
-  protected:
-    /// Constructor
-    BranchExchange(const char *mnem, ExtMachInst _machInst,
-                           OpClass __opClass)
-        : PredOp(mnem, _machInst, __opClass)
-    {
-    }
-
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
 }
 
 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 62a6e40c2..63bb11227 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -84,79 +84,3 @@ def format ArmBlxReg() {{
                           (ConditionCode)(uint32_t)machInst.condCode);
     '''
 }};
-
-def format Branch(code,*opt_flags) {{
-
-    #Build Instruction Flags
-    #Use Link & Likely Flags to Add Link/Condition Code
-    inst_flags = ('IsDirectControl', )
-    linking = False
-    for x in opt_flags:
-        if x == 'Link':
-            linking = True
-            code += 'LR = NPC;\n'
-        else:
-            inst_flags += (x, )
-
-    #Take into account uncond. branch instruction
-    if 'cond == 1' in code:
-         inst_flags += ('IsUnCondControl', )
-    else:
-         inst_flags += ('IsCondControl', )
-
-    icode =  'if (testPredicate(CondCodes, condCode)) {\n'
-    icode += code
-    icode += '  NPC = NPC + 4 + disp;\n'
-    icode += '} else {\n'
-    icode += '  NPC = NPC;\n'
-    if linking:
-        icode += '  LR = LR;\n'
-    icode += '};\n'
-
-    code = icode
-
-    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = BasicExecute.subst(iop)
-}};
-
-def format BranchExchange(code,*opt_flags) {{
-    #Build Instruction Flags
-    #Use Link & Likely Flags to Add Link/Condition Code
-    inst_flags = ('IsIndirectControl', )
-    linking = False
-    for x in opt_flags:
-        if x == 'Link':
-            linking = True
-            code += 'LR = NPC;\n'
-        else:
-            inst_flags += (x, )
-
-    #Take into account uncond. branch instruction
-    if 'cond == 1' in code:
-         inst_flags += ('IsUnCondControl', )
-    else:
-         inst_flags += ('IsCondControl', )
-
-    #Condition code
-
-    icode =  'if (testPredicate(CondCodes, condCode)) {\n'
-    icode += code
-    icode += '  NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
-    icode += '} else {\n'
-    icode += '  NPC = NPC;\n'
-    if linking:
-        icode += '  LR = LR;\n'
-    icode += '};\n'
-
-    code = icode
-
-    iop = InstObjParams(name, Name, 'BranchExchange', code, inst_flags)
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = BasicExecute.subst(iop)
-}};
-