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X86: Fix condition code setting for signed multiplies with negative results.

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This commit is contained in:
Gabe Black 2009-08-05 03:07:01 -07:00
parent 2914a8eb16
commit b64d0bdeda
2 changed files with 51 additions and 42 deletions
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72
src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py
View file

@ -61,26 +61,26 @@ microcode = '''
def macroop MUL_B_R def macroop MUL_B_R
{ {
mul1u rax, reg mul1u rax, reg, flags=(OF,CF)
mulel rax mulel rax
muleh ah, flags=(OF,CF) muleh ah
}; };
def macroop MUL_B_M def macroop MUL_B_M
{ {
ld t1, seg, sib, disp ld t1, seg, sib, disp
mul1u rax, t1 mul1u rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh ah, flags=(OF,CF) muleh ah
}; };
def macroop MUL_B_P def macroop MUL_B_P
{ {
rdip t7 rdip t7
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
mul1u rax, t1 mul1u rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh ah, flags=(OF,CF) muleh ah
}; };
# #
@ -89,26 +89,26 @@ def macroop MUL_B_P
def macroop MUL_R def macroop MUL_R
{ {
mul1u rax, reg mul1u rax, reg, flags=(OF,CF)
mulel rax mulel rax
muleh rdx, flags=(OF,CF) muleh rdx
}; };
def macroop MUL_M def macroop MUL_M
{ {
ld t1, seg, sib, disp ld t1, seg, sib, disp
mul1u rax, t1 mul1u rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh rdx, flags=(OF,CF) muleh rdx
}; };
def macroop MUL_P def macroop MUL_P
{ {
rdip t7 rdip t7
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
mul1u rax, t1 mul1u rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh rdx, flags=(OF,CF) muleh rdx
}; };
# #
@ -117,26 +117,26 @@ def macroop MUL_P
def macroop IMUL_B_R def macroop IMUL_B_R
{ {
mul1s rax, reg mul1s rax, reg, flags=(OF,CF)
mulel rax mulel rax
muleh ah, flags=(OF,CF) muleh ah
}; };
def macroop IMUL_B_M def macroop IMUL_B_M
{ {
ld t1, seg, sib, disp ld t1, seg, sib, disp
mul1s rax, t1 mul1s rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh ah, flags=(OF,CF) muleh ah
}; };
def macroop IMUL_B_P def macroop IMUL_B_P
{ {
rdip t7 rdip t7
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
mul1s rax, t1 mul1s rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh ah, flags=(OF,CF) muleh ah
}; };
# #
@ -145,50 +145,50 @@ def macroop IMUL_B_P
def macroop IMUL_R def macroop IMUL_R
{ {
mul1s rax, reg mul1s rax, reg, flags=(OF,CF)
mulel rax mulel rax
muleh rdx, flags=(OF,CF) muleh rdx
}; };
def macroop IMUL_M def macroop IMUL_M
{ {
ld t1, seg, sib, disp ld t1, seg, sib, disp
mul1s rax, t1 mul1s rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh rdx, flags=(OF,CF) muleh rdx
}; };
def macroop IMUL_P def macroop IMUL_P
{ {
rdip t7 rdip t7
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
mul1s rax, t1 mul1s rax, t1, flags=(OF,CF)
mulel rax mulel rax
muleh rdx, flags=(OF,CF) muleh rdx
}; };
def macroop IMUL_R_R def macroop IMUL_R_R
{ {
mul1s reg, regm mul1s reg, regm, flags=(OF,CF)
mulel reg mulel reg
muleh t0, flags=(CF,OF) muleh t0
}; };
def macroop IMUL_R_M def macroop IMUL_R_M
{ {
ld t1, seg, sib, disp ld t1, seg, sib, disp
mul1s reg, t1 mul1s reg, t1, flags=(CF,OF)
mulel reg mulel reg
muleh t0, flags=(CF,OF) muleh t0
}; };
def macroop IMUL_R_P def macroop IMUL_R_P
{ {
rdip t7 rdip t7
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
mul1s reg, t1 mul1s reg, t1, flags=(CF,OF)
mulel reg mulel reg
muleh t0, flags=(CF,OF) muleh t0
}; };
# #
@ -198,18 +198,18 @@ def macroop IMUL_R_P
def macroop IMUL_R_R_I def macroop IMUL_R_R_I
{ {
limm t1, imm limm t1, imm
mul1s regm, t1 mul1s regm, t1, flags=(OF,CF)
mulel reg mulel reg
muleh t0, flags=(OF,CF) muleh t0
}; };
def macroop IMUL_R_M_I def macroop IMUL_R_M_I
{ {
limm t1, imm limm t1, imm
ld t2, seg, sib, disp ld t2, seg, sib, disp
mul1s t2, t1 mul1s t2, t1, flags=(OF,CF)
mulel reg mulel reg
muleh t0, flags=(OF,CF) muleh t0
}; };
def macroop IMUL_R_P_I def macroop IMUL_R_P_I
@ -217,9 +217,9 @@ def macroop IMUL_R_P_I
rdip t7 rdip t7
limm t1, imm limm t1, imm
ld t2, seg, riprel ld t2, seg, riprel
mul1s t2, t1 mul1s t2, t1, flags=(OF,CF)
mulel reg mulel reg
muleh t0, flags=(OF,CF) muleh t0
}; };
# #

21
src/arch/x86/isa/microops/regop.isa
View file

@ -536,6 +536,14 @@ let {{
hiResult -= psrc1; hiResult -= psrc1;
ProdHi = hiResult; ProdHi = hiResult;
''' '''
flag_code = '''
if ((-ProdHi & mask(dataSize * 8)) !=
bits(ProdLow, dataSize * 8 - 1)) {
ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
} else {
ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
}
'''
class Mul1u(WrRegOp): class Mul1u(WrRegOp):
code = ''' code = '''
@ -550,6 +558,13 @@ let {{
((psrc1_l * psrc2_l) / shifter)) / shifter) + ((psrc1_l * psrc2_l) / shifter)) / shifter) +
psrc1_h * psrc2_h; psrc1_h * psrc2_h;
''' '''
flag_code = '''
if (ProdHi) {
ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
} else {
ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
}
'''
class Mulel(RdRegOp): class Mulel(RdRegOp):
code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
@ -561,12 +576,6 @@ let {{
super(RdRegOp, self).__init__(dest, src1, \ super(RdRegOp, self).__init__(dest, src1, \
"InstRegIndex(NUM_INTREGS)", flags, dataSize) "InstRegIndex(NUM_INTREGS)", flags, dataSize)
code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
flag_code = '''
if (ProdHi)
ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
else
ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
'''
# One or two bit divide # One or two bit divide
class Div1(WrRegOp): class Div1(WrRegOp):