Implement a stub nnpc for alpha that is read only as npc+4.

--HG--
extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d

src/arch/alpha/regfile.hh

@@ -78,13 +78,11 @@ namespace AlphaISA
 
         Addr readNextNPC()
         {
-            return nnpc;
+            return npc + sizeof(MachInst);
         }
 
         void setNextNPC(Addr val)
-        {
+        { }
-            nnpc = val;
-        }
 
       protected:
         IntRegFile intRegFile;		// (signed) integer register file

src/cpu/base_dyn_inst.hh

@@ -209,6 +209,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** PC of this instruction. */
     Addr PC;
 
+  protected:
     /** Next non-speculative PC.  It is not filled in at fetch, but rather
      *  once the target of the branch is truly known (either decode or
      *  execute).
@@ -227,6 +228,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** If this is a branch that was predicted taken */
     bool predTaken;
 
+  public:
+
     /** Count of total number of dynamic instructions. */
     static int instcount;
 
@@ -390,7 +393,14 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Returns the next NPC.  This could be the speculative next NPC if it is
      *  called prior to the actual branch target being calculated.
      */
-    Addr readNextNPC() { return nextNPC; }
+    Addr readNextNPC()
+    {
+#if ISA_HAS_DELAY_SLOT
+        return nextNPC;
+#else
+        return nextPC + sizeof(TheISA::MachInst);
+#endif
+    }
 
     /** Set the predicted target of this current instruction. */
     void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
@@ -419,7 +429,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Returns whether the instruction mispredicted. */
     bool mispredicted()
     {
-        return predPC != nextPC || predNPC != nextNPC;
+        return readPredPC() != readNextPC() ||
+            readPredNPC() != readNextNPC();
     }
 
     //

src/cpu/o3/alpha/thread_context.hh

@@ -45,8 +45,7 @@ class AlphaTC : public O3ThreadContext<Impl>
 
     virtual uint64_t readNextNPC()
     {
-        panic("Alpha has no NextNPC!");
+        return this->readNextPC() + sizeof(TheISA::MachInst);
-        return 0;
     }
 
     virtual void setNextNPC(uint64_t val)

src/cpu/o3/cpu.cc

@@ -659,9 +659,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
     //Set PC/NPC/NNPC
     setPC(src_tc->readPC(), tid);
     setNextPC(src_tc->readNextPC(), tid);
-#if ISA_HAS_DELAY_SLOT
     setNextNPC(src_tc->readNextNPC(), tid);
-#endif
 
     src_tc->setStatus(ThreadContext::Active);
 

src/cpu/ozone/cpu.hh

@@ -219,11 +219,19 @@ class OzoneCPU : public BaseCPU
 
         uint64_t readNextNPC()
         {
-            return 0;
+#if ISA_HAS_DELAY_SLOT
+            panic("Ozone needs to support nextNPC");
+#else
+            return thread->nextPC + sizeof(TheISA::MachInst);
+#endif
         }
 
         void setNextNPC(uint64_t val)
-        { }
+        {
+#if ISA_HAS_DELAY_SLOT
+            panic("Ozone needs to support nextNPC");
+#endif
+        }
 
       public:
         // ISA stuff: