Implement a stub nnpc for alpha that is read only as npc+4.
--HG-- extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
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9ca6efdb60
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5 changed files with 26 additions and 12 deletions
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@ -78,13 +78,11 @@ namespace AlphaISA
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Addr readNextNPC()
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Addr readNextNPC()
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{
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{
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return nnpc;
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return npc + sizeof(MachInst);
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}
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}
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void setNextNPC(Addr val)
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void setNextNPC(Addr val)
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{
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{ }
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nnpc = val;
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}
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protected:
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protected:
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IntRegFile intRegFile; // (signed) integer register file
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IntRegFile intRegFile; // (signed) integer register file
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@ -209,6 +209,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** PC of this instruction. */
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/** PC of this instruction. */
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Addr PC;
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Addr PC;
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protected:
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/** Next non-speculative PC. It is not filled in at fetch, but rather
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/** Next non-speculative PC. It is not filled in at fetch, but rather
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* once the target of the branch is truly known (either decode or
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* once the target of the branch is truly known (either decode or
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* execute).
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* execute).
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@ -227,6 +228,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** If this is a branch that was predicted taken */
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/** If this is a branch that was predicted taken */
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bool predTaken;
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bool predTaken;
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public:
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/** Count of total number of dynamic instructions. */
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/** Count of total number of dynamic instructions. */
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static int instcount;
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static int instcount;
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@ -390,7 +393,14 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Returns the next NPC. This could be the speculative next NPC if it is
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/** Returns the next NPC. This could be the speculative next NPC if it is
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* called prior to the actual branch target being calculated.
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* called prior to the actual branch target being calculated.
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*/
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*/
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Addr readNextNPC() { return nextNPC; }
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Addr readNextNPC()
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{
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#if ISA_HAS_DELAY_SLOT
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return nextNPC;
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#else
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return nextPC + sizeof(TheISA::MachInst);
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#endif
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}
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/** Set the predicted target of this current instruction. */
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/** Set the predicted target of this current instruction. */
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void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
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void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
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@ -419,7 +429,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Returns whether the instruction mispredicted. */
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/** Returns whether the instruction mispredicted. */
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bool mispredicted()
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bool mispredicted()
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{
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{
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return predPC != nextPC || predNPC != nextNPC;
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return readPredPC() != readNextPC() ||
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readPredNPC() != readNextNPC();
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}
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}
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//
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//
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@ -45,8 +45,7 @@ class AlphaTC : public O3ThreadContext<Impl>
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virtual uint64_t readNextNPC()
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virtual uint64_t readNextNPC()
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{
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{
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panic("Alpha has no NextNPC!");
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return this->readNextPC() + sizeof(TheISA::MachInst);
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return 0;
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}
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}
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virtual void setNextNPC(uint64_t val)
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virtual void setNextNPC(uint64_t val)
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@ -659,9 +659,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
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//Set PC/NPC/NNPC
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//Set PC/NPC/NNPC
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setPC(src_tc->readPC(), tid);
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setPC(src_tc->readPC(), tid);
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setNextPC(src_tc->readNextPC(), tid);
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setNextPC(src_tc->readNextPC(), tid);
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#if ISA_HAS_DELAY_SLOT
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setNextNPC(src_tc->readNextNPC(), tid);
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setNextNPC(src_tc->readNextNPC(), tid);
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#endif
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src_tc->setStatus(ThreadContext::Active);
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src_tc->setStatus(ThreadContext::Active);
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@ -219,11 +219,19 @@ class OzoneCPU : public BaseCPU
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uint64_t readNextNPC()
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uint64_t readNextNPC()
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{
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{
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return 0;
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#if ISA_HAS_DELAY_SLOT
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panic("Ozone needs to support nextNPC");
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#else
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return thread->nextPC + sizeof(TheISA::MachInst);
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#endif
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}
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}
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void setNextNPC(uint64_t val)
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void setNextNPC(uint64_t val)
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{ }
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{
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#if ISA_HAS_DELAY_SLOT
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panic("Ozone needs to support nextNPC");
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#endif
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}
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public:
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public:
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// ISA stuff:
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// ISA stuff:
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