ARM: Convert the CP15 registers from MPU to MMU.

src/arch/arm/isa.hh

@@ -116,9 +116,6 @@ namespace ArmISA
             cpacr.cp11 = 0x3;
             miscRegs[MISCREG_CPACR] = cpacr;
 
-            /* One region, unified map. */
-            miscRegs[MISCREG_MPUIR] = 0x100;
-
             /* Start with an event in the mailbox */
             miscRegs[MISCREG_SEV_MAILBOX] = 1;
 

src/arch/arm/isa/formats/misc.isa

@@ -128,15 +128,6 @@ def format McrMrc15() {{
           case MISCREG_BPIALL:
             return new WarnUnimplemented(
                     isRead ? "mrc bpiall" : "mcr bpiall", machInst);
-          case MISCREG_DRBAR:
-            return new WarnUnimplemented(
-                    isRead ? "mrc drbar" : "mcr drbar", machInst);
-          case MISCREG_DRACR:
-            return new WarnUnimplemented(
-                    isRead ? "mrc dracr" : "mcr dracr", machInst);
-          case MISCREG_DRSR:
-            return new WarnUnimplemented(
-                    isRead ? "mrc drsr" : "mcr drsr", machInst);
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

src/arch/arm/miscregs.cc

@@ -56,8 +56,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                     return MISCREG_CTR;
                   case 2:
                     return MISCREG_TCMTR;
-                  case 4:
+                  case 3:
-                    return MISCREG_MPUIR;
+                    return MISCREG_TLBTR;
                   case 5:
                     return MISCREG_MPIDR;
                   default:
@@ -127,7 +127,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         }
         break;
       case 1:
-        if (opc1 == 0 && crm == 0) {
+        if (opc1 == 0) {
+            if (crm == 0) {
                 switch (opc2) {
                   case 0:
                     return MISCREG_SCTLR;
@@ -136,6 +137,33 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                   case 0x2:
                     return MISCREG_CPACR;
                 }
+            } else if (crm == 1) {
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_SCR;
+                  case 1:
+                    return MISCREG_SDER;
+                  case 2:
+                    return MISCREG_NSACR;
+                }
+            }
+        }
+        break;
+      case 2:
+        if (opc2 == 0 && crm == 0) {
+            switch (opc2) {
+              case 0:
+                return MISCREG_TTBR0;
+              case 1:
+                return MISCREG_TTBR1;
+              case 2:
+                return MISCREG_TTBCR;
+            }
+        }
+        break;
+      case 3:
+        if (opc1 == 0 && crm == 0 && opc2 == 0) {
+            return MISCREG_DACR;
         }
         break;
       case 5:
@@ -156,37 +184,13 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         }
         break;
       case 6:
-        if (opc1 == 0) {
+        if (opc1 == 0 && crm == 0) {
-            switch (crm) {
-              case 0:
             switch (opc2) {
               case 0:
                 return MISCREG_DFAR;
               case 2:
                 return MISCREG_IFAR;
             }
-                break;
-              case 1:
-                switch (opc2) {
-                  case 0:
-                    return MISCREG_DRBAR;
-                  case 1:
-                    return MISCREG_IRBAR;
-                  case 2:
-                    return MISCREG_DRSR;
-                  case 3:
-                    return MISCREG_IRSR;
-                  case 4:
-                    return MISCREG_DRACR;
-                  case 5:
-                    return MISCREG_IRACR;
-                }
-                break;
-              case 2:
-                if (opc2 == 0) {
-                    return MISCREG_RGNR;
-                }
-            }
         }
         break;
       case 7:
@@ -205,6 +209,11 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                     return MISCREG_BPIALLIS;
                 }
                 break;
+              case 4:
+                if (opc2 == 0) {
+                    return MISCREG_PAR;
+                }
+                break;
               case 5:
                 switch (opc2) {
                   case 0:
@@ -226,6 +235,26 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                     return MISCREG_DCISW;
                 }
                 break;
+              case 8:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_V2PCWPR;
+                  case 1:
+                    return MISCREG_V2PCWPW;
+                  case 2:
+                    return MISCREG_V2PCWUR;
+                  case 3:
+                    return MISCREG_V2PCWUW;
+                  case 4:
+                    return MISCREG_V2POWPR;
+                  case 5:
+                    return MISCREG_V2POWPW;
+                  case 6:
+                    return MISCREG_V2POWUR;
+                  case 7:
+                    return MISCREG_V2POWUW;
+                }
+                break;
               case 10:
                 switch (opc2) {
                   case 1:
@@ -258,6 +287,56 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
             }
         }
         break;
+      case 8:
+        if (opc1 == 0) {
+            switch (crm) {
+              case 3:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_TLBIALLIS;
+                  case 1:
+                    return MISCREG_TLBIMVAIS;
+                  case 2:
+                    return MISCREG_TLBIASIDIS;
+                  case 3:
+                    return MISCREG_TLBIMVAAIS;
+                }
+                break;
+              case 5:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_ITLBIALL;
+                  case 1:
+                    return MISCREG_ITLBIMVA;
+                  case 2:
+                    return MISCREG_ITLBIASID;
+                }
+                break;
+              case 6:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_DTLBIALL;
+                  case 1:
+                    return MISCREG_DTLBIMVA;
+                  case 2:
+                    return MISCREG_DTLBIASID;
+                }
+                break;
+              case 7:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_TLBIALL;
+                  case 1:
+                    return MISCREG_TLBIMVA;
+                  case 2:
+                    return MISCREG_TLBIASID;
+                  case 3:
+                    return MISCREG_TLBIMVAA;
+                }
+                break;
+            }
+        }
+        break;
       case 9:
         if (opc1 >= 0 && opc1 <= 7) {
             switch (crm) {
@@ -278,6 +357,18 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
             }
         }
         break;
+      case 10:
+        if (opc1 == 0) {
+            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
+            if (crm == 2) { // TEX Remap Registers
+                if (opc2 == 0) {
+                    return MISCREG_PRRR;
+                } else if (opc2 == 1) {
+                    return MISCREG_NMRR;
+                }
+            }
+        }
+        break;
       case 11:
         if (opc1 >= 0 && opc1 <=7) {
             switch (crm) {
@@ -296,10 +387,27 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
             }
         }
         break;
+      case 12:
+        if (opc1 == 0) {
+            if (crm == 0) {
+                if (opc2 == 0) {
+                    return MISCREG_VBAR;
+                } else if (opc2 == 1) {
+                    return MISCREG_MVBAR;
+                }
+            } else if (crm == 1) {
+                if (opc2 == 0) {
+                    return MISCREG_ISR;
+                }
+            }
+        }
+        break;
       case 13:
         if (opc1 == 0) {
             if (crm == 0) {
                 switch (crm) {
+                  case 0:
+                    return MISCREG_FCEIDR;
                   case 1:
                     return MISCREG_CONTEXTIDR;
                   case 2:

src/arch/arm/miscregs.hh

@@ -105,14 +105,10 @@ namespace ArmISA
         MISCREG_BPIMVA,
         MISCREG_BPIALLIS,
         MISCREG_BPIALL,
-        MISCREG_MPUIR,
         MISCREG_MIDR,
-        MISCREG_RGNR,
-        MISCREG_DRBAR,
-        MISCREG_DRACR,
-        MISCREG_DRSR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
+        MISCREG_TLBTR,
         MISCREG_TCMTR,
         MISCREG_MPIDR,
         MISCREG_ID_PFR0,
@@ -129,21 +125,55 @@ namespace ArmISA
         MISCREG_ID_ISAR3,
         MISCREG_ID_ISAR4,
         MISCREG_ID_ISAR5,
+        MISCREG_PAR,
         MISCREG_AIDR,
         MISCREG_ACTLR,
+        MISCREG_DACR,
         MISCREG_DFSR,
         MISCREG_IFSR,
         MISCREG_ADFSR,
         MISCREG_AIFSR,
         MISCREG_DFAR,
         MISCREG_IFAR,
-        MISCREG_IRBAR,
-        MISCREG_IRSR,
-        MISCREG_IRACR,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
         MISCREG_MCCSW,
         MISCREG_DCCMVAU,
+        MISCREG_SCR,
+        MISCREG_SDER,
+        MISCREG_NSACR,
+        MISCREG_TTBR0,
+        MISCREG_TTBR1,
+        MISCREG_TTBCR,
+        MISCREG_V2PCWPR,
+        MISCREG_V2PCWPW,
+        MISCREG_V2PCWUR,
+        MISCREG_V2PCWUW,
+        MISCREG_V2POWPR,
+        MISCREG_V2POWPW,
+        MISCREG_V2POWUR,
+        MISCREG_V2POWUW,
+        MISCREG_TLBIALLIS,
+        MISCREG_TLBIMVAIS,
+        MISCREG_TLBIASIDIS,
+        MISCREG_TLBIMVAAIS,
+        MISCREG_ITLBIALL,
+        MISCREG_ITLBIMVA,
+        MISCREG_ITLBIASID,
+        MISCREG_DTLBIALL,
+        MISCREG_DTLBIMVA,
+        MISCREG_DTLBIASID,
+        MISCREG_TLBIALL,
+        MISCREG_TLBIMVA,
+        MISCREG_TLBIASID,
+        MISCREG_TLBIMVAA,
+        MISCREG_PRRR,
+        MISCREG_NMRR,
+        MISCREG_VBAR,
+        MISCREG_MVBAR,
+        MISCREG_ISR,
+        MISCREG_FCEIDR,
+
 
         MISCREG_CP15_END,
 
@@ -160,23 +190,30 @@ namespace ArmISA
     const char * const miscRegName[NUM_MISCREGS] = {
         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
-        "fpsr", "fpsid", "fpscr", "fpexc", "sev_mailbox",
+        "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
+        "sev_mailbox",
         "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
         "clidr", "ccsidr", "csselr",
         "icialluis", "iciallu", "icimvau",
         "bpimva", "bpiallis", "bpiall",
-        "mpuir", "midr", "rgnr", "drbar", "dracr", "drsr",
+        "midr", "ctr", "tlbtr", "tcmtr", "mpidr",
-        "ctr", "tcmtr", "mpidr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "aidr", "actlr",
+        "par", "aidr", "actlr", "dacr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
-        "irbar", "irsr", "iracr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
+        "scr", "sder", "nsacr", "ttbr0", "ttbr1", "ttbcr",
+        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
+        "v2powpr", "v2powpw", "v2powur", "v2powuw",
+        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
+        "itlbiall", "itlbimva", "itlbiasid",
+        "dtlbiall", "dtlbimva", "dtlbiasid",
+        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
+        "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
         "nop", "raz"
     };