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Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.

Browse source 
src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
    Fixes for checker.

--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
This commit is contained in:
Kevin Lim 2006-06-12 19:11:38 -04:00
parent 6152e8abc3
commit b5cf61efad
2 changed files with 4 additions and 2 deletions
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4
src/arch/alpha/isa/decoder.isa
View file

@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
0xe000: rc({{ 0xe000: rc({{
Ra = xc->readIntrFlag(); Ra = xc->readIntrFlag();
xc->setIntrFlag(0); xc->setIntrFlag(0);
}}, IsNonSpeculative); }}, IsNonSpeculative, IsUnverifiable);
0xf000: rs({{ 0xf000: rs({{
Ra = xc->readIntrFlag(); Ra = xc->readIntrFlag();
xc->setIntrFlag(1); xc->setIntrFlag(1);
}}, IsNonSpeculative); }}, IsNonSpeculative, IsUnverifiable);
} }
#else #else
format FailUnimpl { format FailUnimpl {

2
src/cpu/checker/cpu.cc
View file

@ -84,6 +84,8 @@ CheckerCPU::CheckerCPU(Params *p)
#else #else
process = p->process; process = p->process;
#endif #endif
result.integer = 0;
} }
CheckerCPU::~CheckerCPU() CheckerCPU::~CheckerCPU()