inorder-bpred: edits to handle non-delay-slot ISAs
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
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@ -166,11 +166,11 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
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tc->setPC(prog_entry);
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tc->setNextPC(prog_entry + sizeof(MachInst));
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#if THE_ISA != ALPHA_ISA //e.g. MIPS or Sparc
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// MIPS/Sparc need NNPC for delay slot handling, while
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// Alpha has no delay slots... However, CPU models
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// cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this
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// here ensures CPU-Model Compatibility across board
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tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
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#endif
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}
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void
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@ -264,6 +264,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** Predicted next PC. */
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Addr predPC;
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/** Predicted next NPC. */
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Addr predNPC;
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/** Predicted next microPC */
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Addr predMicroPC;
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/** Address to fetch from */
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Addr fetchAddr;
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@ -506,7 +512,14 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** Returns the next NPC. This could be the speculative next NPC if it is
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* called prior to the actual branch target being calculated.
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*/
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Addr readNextNPC() { return nextNPC; }
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Addr readNextNPC()
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{
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#if ISA_HAS_DELAY_SLOT
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return nextNPC;
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#else
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return nextPC + sizeof(TheISA::MachInst);
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#endif
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}
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/** Set the next PC of this instruction (its actual target). */
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void setNextNPC(uint64_t val) { nextNPC = val; }
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@ -522,19 +535,26 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** Returns the predicted target of the branch. */
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Addr readPredTarg() { return predPC; }
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/** Returns the predicted PC immediately after the branch. */
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Addr readPredPC() { return predPC; }
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/** Returns the predicted PC two instructions after the branch */
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Addr readPredNPC() { return predNPC; }
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/** Returns the predicted micro PC after the branch */
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Addr readPredMicroPC() { return predMicroPC; }
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/** Returns whether the instruction was predicted taken or not. */
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bool predTaken() { return predictTaken; }
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/** Returns whether the instruction mispredicted. */
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bool mispredicted()
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{
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// Special case since a not-taken, cond. delay slot, effectively
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// nullifies the delay slot instruction
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if (isCondDelaySlot() && !predictTaken) {
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return predPC != nextPC;
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} else {
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#if ISA_HAS_DELAY_SLOT
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return predPC != nextNPC;
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}
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#else
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return predPC != nextPC;
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#endif
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}
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/** Returns whether the instruction mispredicted. */
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@ -342,13 +342,21 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, unsigned tid)
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toPrevStages->stageInfo[stageNum][tid].doneSeqNum = inst->seqNum;
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toPrevStages->stageInfo[stageNum][tid].squash = true;
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toPrevStages->stageInfo[stageNum][tid].nextPC = inst->readPredTarg();
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#if ISA_HAS_DELAY_SLOT
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toPrevStages->stageInfo[stageNum][tid].branchTaken = inst->readNextNPC() !=
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(inst->readNextPC() + sizeof(TheISA::MachInst));
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toPrevStages->stageInfo[stageNum][tid].bdelayDoneSeqNum = inst->bdelaySeqNum;
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InstSeqNum squash_seq_num = inst->bdelaySeqNum;
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#else
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toPrevStages->stageInfo[stageNum][tid].branchTaken = inst->readNextPC() !=
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(inst->readPC() + sizeof(TheISA::MachInst));
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toPrevStages->stageInfo[stageNum][tid].bdelayDoneSeqNum = inst->seqNum;
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InstSeqNum squash_seq_num = inst->seqNum;
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#endif
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DPRINTF(InOrderStage, "Target being re-set to %08p\n", inst->readPredTarg());
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InstSeqNum squash_seq_num = inst->bdelaySeqNum;
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DPRINTF(InOrderStage, "[tid:%i]: Squashing after [sn:%i], due to [sn:%i] "
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"branch.\n", tid, squash_seq_num, inst->seqNum);
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@ -248,7 +248,12 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
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PC = target;
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inst->setPredTarg(target);
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} else {
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#if ISA_HAS_DELAY_SLOT
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// This value will be inst->PC + 4 (nextPC)
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// Delay Slot archs need this to be inst->PC + 8 (nextNPC)
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// so we increment one more time here.
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PC = PC + sizeof(MachInst);
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#endif
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inst->setPredTarg(PC);
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}
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@ -78,12 +78,12 @@ BranchPredictor::execute(int slot_num)
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Addr pred_PC = inst->readNextPC();
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if (inst->isControl()) {
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// If predicted, the pred_PC will be updated to new target value
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// If not, the pred_PC be updated to pc+8
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// If predicted, the pred_PC will be updated to new target value
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bool predict_taken = branchPred.predict(inst, pred_PC, tid);
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if (predict_taken) {
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DPRINTF(Resource, "[tid:%i]: [sn:%i]: Branch predicted true.\n",
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DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted true.\n",
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tid, seq_num);
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inst->setPredTarg(pred_PC);
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@ -76,7 +76,7 @@ ExecutionUnit::execute(int slot_num)
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case ExecuteInst:
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{
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if (inst->isMemRef()) {
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fatal("%s not configured to handle memory ops.\n", resName);
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panic("%s not configured to handle memory ops.\n", resName);
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} else if (inst->isControl()) {
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// Evaluate Branch
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fault = inst->execute();
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@ -111,23 +111,33 @@ ExecutionUnit::execute(int slot_num)
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"[sn:%i] PC %#x mispredicted as not taken.\n", tid,
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seq_num, inst->PC);
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} else {
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#if ISA_HAS_DELAY_SLOT
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inst->bdelaySeqNum = seq_num + 1;
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inst->setPredTarg(inst->nextNPC);
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#else
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inst->bdelaySeqNum = seq_num;
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inst->setPredTarg(inst->nextPC);
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#endif
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DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at "
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"[sn:%i] PC %#x,\n\t squashing after delay slot "
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"instruction [sn:%i].\n",
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tid, seq_num, inst->PC, inst->bdelaySeqNum);
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DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch "
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"misprediction at %#x\n", tid, inst->PC);
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inst->setPredTarg(inst->nextNPC);
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}
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DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
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inst->readPredTarg());
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} else if(inst->isIndirectCtrl()){
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#if ISA_HAS_DELAY_SLOT
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inst->setPredTarg(inst->nextNPC);
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inst->bdelaySeqNum = seq_num + 1;
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#else
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inst->setPredTarg(inst->nextPC);
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inst->bdelaySeqNum = seq_num;
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#endif
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DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
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inst->readPredTarg());
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} else {
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@ -151,7 +161,13 @@ ExecutionUnit::execute(int slot_num)
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} else {
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predictedNotTakenIncorrect++;
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}
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} else {
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
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inst->readTid(), seq_num, inst->readIntResult(0));
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}
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
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inst->readTid(), seq_num, inst->readIntResult(0));
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exec_req->done();
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} else {
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warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
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@ -164,8 +180,8 @@ ExecutionUnit::execute(int slot_num)
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inst->setExecuted();
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exec_req->done();
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DPRINTF(InOrderExecute, "[tid:%i]: The result of execution is 0x%x.\n",
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inst->readTid(), inst->readIntResult(0));
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
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inst->readTid(), seq_num, inst->readIntResult(0));
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} else {
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warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
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cpu->trap(fault, tid);
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@ -96,13 +96,16 @@ FetchSeqUnit::execute(int slot_num)
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inst->setNextPC(PC[tid] + instSize);
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inst->setNextNPC(PC[tid] + (instSize * 2));
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#if ISA_HAS_DELAY_SLOT
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inst->setPredTarg(inst->readNextNPC());
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#else
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inst->setPredTarg(inst->readNextPC());
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#endif
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inst->setMemAddr(PC[tid]);
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inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p\n", tid,
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inst->seqNum, inst->readPC());
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p, NPC %08p, NNPC %08p\n", tid,
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inst->seqNum, inst->readPC(), inst->readNextPC(), inst->readNextNPC());
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if (delaySlotInfo[tid].numInsts > 0) {
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--delaySlotInfo[tid].numInsts;
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@ -154,26 +157,33 @@ FetchSeqUnit::execute(int slot_num)
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
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"inst. updating PC to %08p\n", tid, inst->seqNum,
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inst->readNextPC());
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#if ISA_HAS_DELAY_SLOT
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++delaySlotInfo[tid].numInsts;
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delaySlotInfo[tid].targetReady = false;
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delaySlotInfo[tid].targetAddr = inst->readNextNPC();
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#else
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assert(delaySlotInfo[tid].numInsts == 0);
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#endif
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} else if (inst->predTaken()) {
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// Taken Control
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#if ISA_HAS_DELAY_SLOT
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++delaySlotInfo[tid].numInsts;
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delaySlotInfo[tid].targetReady = false;
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delaySlotInfo[tid].targetAddr = inst->readPredTarg();
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target "
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"to PC %08p\n", tid, inst->seqNum, inst->readPredTarg());
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// Set-Up Squash Through-Out Pipeline
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DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
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tid, stage_num, seq_num + 1);
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inst->bdelaySeqNum = seq_num + 1;
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#else
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inst->bdelaySeqNum = seq_num;
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assert(delaySlotInfo[tid].numInsts == 0);
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#endif
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inst->squashingStage = stage_num;
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DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
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tid, stage_num, inst->bdelaySeqNum);
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// Do Squashing
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squashAfterInst(inst, stage_num, tid);
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}
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@ -239,6 +249,10 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
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tid, PC[tid]);
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} else {
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#if !ISA_HAS_DELAY_SLOT
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assert(0);
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#endif
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delaySlotInfo[tid].numInsts = 1;
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delaySlotInfo[tid].targetReady = false;
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delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ? inst->branchTarget() : new_PC;
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@ -265,9 +265,6 @@ class O3ThreadContext : public ThreadContext
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virtual void setNextNPC(uint64_t val)
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{
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#if THE_ISA == ALPHA_ISA
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panic("Not supported on Alpha!");
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#endif
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this->cpu->setNextNPC(val, this->thread->threadId());
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}
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};
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