Split out alpha integer register file into it's own files.
--HG-- extra : convert_revision : 164bdcec2860c5dca3f0f11d189781b88dd717cb
This commit is contained in:
parent
71dc49c785
commit
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5 changed files with 140 additions and 35 deletions
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@ -50,6 +50,7 @@ base_sources = Split('''
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faults.cc
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faults.cc
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isa_traits.cc
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isa_traits.cc
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miscregfile.cc
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miscregfile.cc
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intregfile.cc
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''')
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''')
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# Full-system sources
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# Full-system sources
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65
src/arch/alpha/intregfile.cc
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65
src/arch/alpha/intregfile.cc
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@ -0,0 +1,65 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Gabe Black
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* Kevin Lim
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*/
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/intregfile.hh"
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#include "sim/serialize.hh"
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namespace AlphaISA
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{
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#if FULL_SYSTEM
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const int reg_redir[AlphaISA::NumIntRegs] = {
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/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
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/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
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/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
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/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
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#else
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const int reg_redir[AlphaISA::NumIntRegs] = {
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/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
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/* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
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/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
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/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
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#endif
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void
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IntRegFile::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(regs, NumIntRegs);
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}
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void
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IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(regs, NumIntRegs);
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}
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}
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73
src/arch/alpha/intregfile.hh
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73
src/arch/alpha/intregfile.hh
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@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Gabe Black
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*/
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#ifndef __ARCH_ALPHA_INTREGFILE_HH__
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#define __ARCH_ALPHA_INTREGFILE_HH__
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#include "arch/alpha/types.hh"
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#include <iostream>
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#include <strings.h>
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class Checkpoint;
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namespace AlphaISA
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{
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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class IntRegFile
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{
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protected:
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IntReg regs[NumIntRegs];
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public:
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IntReg readReg(int intReg)
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{
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return regs[intReg];
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}
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void setReg(int intReg, const IntReg &val)
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{
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regs[intReg] = val;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void clear()
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{ bzero(regs, sizeof(regs)); }
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};
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}
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#endif
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@ -114,7 +114,6 @@ namespace AlphaISA
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NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
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NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
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};
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};
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// EV5 modes
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// EV5 modes
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enum mode_type
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enum mode_type
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{
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{
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@ -181,9 +180,6 @@ namespace AlphaISA
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// Alpha UNOP (ldq_u r31,0(r0))
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// Alpha UNOP (ldq_u r31,0(r0))
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const ExtMachInst NoopMachInst = 0x2ffe0000;
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const ExtMachInst NoopMachInst = 0x2ffe0000;
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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};
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};
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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@ -32,7 +32,7 @@
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#define __ARCH_ALPHA_REGFILE_HH__
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#define __ARCH_ALPHA_REGFILE_HH__
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/ipr.hh"
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#include "arch/alpha/intregfile.hh"
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#include "arch/alpha/miscregfile.hh"
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#include "arch/alpha/miscregfile.hh"
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#include "arch/alpha/types.hh"
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#include "arch/alpha/types.hh"
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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@ -62,32 +62,6 @@ namespace AlphaISA
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return "";
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return "";
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}
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}
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class IntRegFile
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{
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protected:
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IntReg regs[NumIntRegs];
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public:
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IntReg readReg(int intReg)
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{
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return regs[intReg];
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}
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Fault setReg(int intReg, const IntReg &val)
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{
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regs[intReg] = val;
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return NoFault;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void clear()
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{ bzero(regs, sizeof(regs)); }
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};
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class FloatRegFile
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class FloatRegFile
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{
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{
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public:
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public:
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@ -249,10 +223,6 @@ namespace AlphaISA
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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#if FULL_SYSTEM
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void copyIprs(ThreadContext *src, ThreadContext *dest);
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#endif
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} // namespace AlphaISA
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} // namespace AlphaISA
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#endif
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#endif
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