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ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.

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This commit is contained in:
Ali Saidi 2010-11-08 13:58:24 -06:00
parent cdacbe734a
commit b4b6a2338a
109 changed files with 3795 additions and 5556 deletions
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4
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

14
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:56:01
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:21:55
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -44,4 +46,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 165376986500 because target called exit()
Exiting @ tick 162779779500 because target called exit()

642
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,339 +1,339 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 264030 # Simulator instruction rate (inst/s)
host_mem_usage 193748 # Number of bytes of host memory used
host_seconds 2142.00 # Real time elapsed on the host
host_tick_rate 77206740 # Simulator tick rate (ticks/s)
host_inst_rate 299092 # Simulator instruction rate (inst/s)
host_mem_usage 240504 # Number of bytes of host memory used
host_seconds 1890.90 # Real time elapsed on the host
host_tick_rate 86086026 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.165377 # Number of seconds simulated
sim_ticks 165376986500 # Number of ticks simulated
sim_seconds 0.162780 # Number of seconds simulated
sim_ticks 162779779500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 63926991 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 71320793 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 193 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 4120736 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 70355271 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 76295210 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1675650 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 19927815 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 315794082 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.905853 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.338192 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 102454006 32.44% 32.44% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 100543040 31.84% 64.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 36844526 11.67% 75.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 9307171 2.95% 78.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10247874 3.25% 82.14% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 21736977 6.88% 89.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 12524254 3.97% 92.99% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2208419 0.70% 93.69% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 19927815 6.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 # Number of instructions committed
system.cpu.commit.COM:loads 115049510 # Number of loads committed
system.cpu.commit.COM:loads 114514042 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:refs 153965363 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 4119890 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 60520337 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses
system.cpu.cpi 0.575649 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.575649 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 112312480 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15160.742892 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7367.811163 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 111525313 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11934036500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 787167 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 569138 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1606396500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001941 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 218029 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 14279.189894 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11300.460826 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 38165820 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 18355912888 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.032584 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1285501 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1028584 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2903280494 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_misses 256917 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.150943 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked
system.cpu.dcache.avg_refs 315.175064 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 773498 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 151763801 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14613.989982 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency
system.cpu.dcache.demand_hits 149691133 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 30289949388 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.013657 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2072668 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1597722 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4509676994 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003130 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 474946 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.999550 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.156298 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 151763801 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14613.989982 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 152530559 # number of overall hits
system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1933689 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses
system.cpu.dcache.overall_hits 149691133 # number of overall hits
system.cpu.dcache.overall_miss_latency 30289949388 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.013657 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2072668 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1597722 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4509676994 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003130 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 474946 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 471004 # number of replacements
system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 470850 # number of replacements
system.cpu.dcache.sampled_refs 474946 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use
system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 423151 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 163094811 # DTB accesses
system.cpu.dcache.tagsinuse 4094.156298 # Cycle average of tags in use
system.cpu.dcache.total_refs 149691136 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126698000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 423042 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 45000094 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 877 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4176202 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 688674202 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 142513181 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 122905016 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 9698747 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 3338 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5375791 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 163053496 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 163045966 # DTB hits
system.cpu.dtb.data_misses 48845 # DTB misses
system.cpu.dtb.data_hits 163001268 # DTB hits
system.cpu.dtb.data_misses 52228 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 122278185 # DTB read accesses
system.cpu.dtb.read_accesses 122206073 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 122255138 # DTB read hits
system.cpu.dtb.read_misses 23047 # DTB read misses
system.cpu.dtb.write_accesses 40816626 # DTB write accesses
system.cpu.dtb.read_hits 122181392 # DTB read hits
system.cpu.dtb.read_misses 24681 # DTB read misses
system.cpu.dtb.write_accesses 40847423 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 40790828 # DTB write hits
system.cpu.dtb.write_misses 25798 # DTB write misses
system.cpu.fetch.Branches 76396550 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65649275 # Number of cache lines fetched
system.cpu.fetch.Cycles 195872330 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1325100 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 699185184 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4170349 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.230977 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65649275 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 65605896 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.113913 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 330660336 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.114512 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.085107 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 40819876 # DTB write hits
system.cpu.dtb.write_misses 27547 # DTB write misses
system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched
system.cpu.fetch.Cycles 195638983 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 65602641 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.143680 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 325492829 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.144120 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.095910 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 200437318 60.62% 60.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10372140 3.14% 63.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15863919 4.80% 68.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13948828 4.22% 72.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12077397 3.65% 76.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13850642 4.19% 80.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5888624 1.78% 82.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3427564 1.04% 83.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 54793904 16.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 195414198 60.04% 60.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10425646 3.20% 63.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15856104 4.87% 68.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13952359 4.29% 72.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12095872 3.72% 76.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13761061 4.23% 80.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5876732 1.81% 82.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3435361 1.06% 83.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 54675496 16.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 330660336 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 65649275 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36269.949066 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 65648097 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 42726000 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 65559135 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 42777500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1178 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 268 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32327500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 1180 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32318500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 72140.765934 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 72043.005495 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 65649275 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36269.949066 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
system.cpu.icache.demand_hits 65648097 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 42726000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 65560315 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36252.118644 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency
system.cpu.icache.demand_hits 65559135 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 42777500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
system.cpu.icache.demand_misses 1178 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 268 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32327500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 1180 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32318500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.378879 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 775.944948 # Average occupied blocks per context
system.cpu.icache.overall_accesses 65649275 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36269.949066 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.378389 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 774.939822 # Average occupied blocks per context
system.cpu.icache.overall_accesses 65560315 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36252.118644 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 65648097 # number of overall hits
system.cpu.icache.overall_miss_latency 42726000 # number of overall miss cycles
system.cpu.icache.overall_hits 65559135 # number of overall hits
system.cpu.icache.overall_miss_latency 42777500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
system.cpu.icache.overall_misses 1178 # number of overall misses
system.cpu.icache.overall_mshr_hits 268 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32327500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 1180 # number of overall misses
system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32318500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 32 # number of replacements
system.cpu.icache.replacements 34 # number of replacements
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 775.944948 # Cycle average of tags in use
system.cpu.icache.total_refs 65648097 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 774.939822 # Cycle average of tags in use
system.cpu.icache.total_refs 65559135 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 93638 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67433622 # Number of branches executed
system.cpu.iew.EXEC:nop 43234709 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.811577 # Inst execution rate
system.cpu.iew.EXEC:refs 164032675 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41211382 # Number of stores executed
system.cpu.idleCycles 66731 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67424273 # Number of branches executed
system.cpu.iew.EXEC:nop 43222760 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.839913 # Inst execution rate
system.cpu.iew.EXEC:refs 163081324 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 40875188 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 492720055 # num instructions consuming a value
system.cpu.iew.WB:count 595983189 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.807592 # average fanout of values written-back
system.cpu.iew.WB:consumers 487722865 # num instructions consuming a value
system.cpu.iew.WB:count 595805949 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811742 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 397916939 # num instructions producing a value
system.cpu.iew.WB:rate 1.801893 # insts written-back per cycle
system.cpu.iew.WB:sent 597091543 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4603878 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1505457 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 126939472 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3143406 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 43126164 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 663744184 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 122821293 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6299898 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 599186314 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2121 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 395904949 # num instructions producing a value
system.cpu.iew.WB:rate 1.830098 # insts written-back per cycle
system.cpu.iew.WB:sent 596918670 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4602797 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1364972 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 126095826 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3115345 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 42628898 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 662516409 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 122206136 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6268247 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 599001166 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 43958 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 28444 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 9844039 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 43665 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 13859 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 9698747 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 63343 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 720 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 7235686 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 12544 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 729 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 9862373 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 10156 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 71476 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5929 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 11889962 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3313641 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 71476 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 943110 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3660768 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.709889 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.709889 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 70243 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5936 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 11581784 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3177577 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 438748901 72.46% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 124774485 20.61% 93.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956101 6.93% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 439513912 72.61% 72.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 124151932 20.51% 93.13% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41596836 6.87% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 605486212 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 7206090 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 605269413 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 7095490 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011723 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5226098 72.52% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 1579159 21.91% 94.44% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 400785 5.56% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5209273 73.42% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 47 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 73.42% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 1541723 21.73% 95.15% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 344447 4.85% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 330660336 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.831143 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.672265 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 325492829 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.859548 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.691188 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 90539952 27.38% 27.38% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 66701453 20.17% 47.55% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 79600053 24.07% 71.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 36541170 11.05% 82.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 31317153 9.47% 92.15% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 13281184 4.02% 96.17% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 11041150 3.34% 99.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1066057 0.32% 99.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 572164 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 87236535 26.80% 26.80% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 66508902 20.43% 47.23% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 78677146 24.17% 71.41% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 34244703 10.52% 81.93% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 30387182 9.34% 91.26% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 15745565 4.84% 96.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 11042338 3.39% 99.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1062135 0.33% 99.82% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 588323 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 330660336 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.830624 # Inst issue rate
system.cpu.iq.iqInstsAdded 620509446 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 605486212 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 53535562 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 17232 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 29599324 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate
system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 52323110 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12647 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 28040159 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 65649312 # ITB accesses
system.cpu.itb.fetch_accesses 65560352 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 65649275 # ITB hits
system.cpu.itb.fetch_hits 65560315 # ITB hits
system.cpu.itb.fetch_misses 37 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -343,98 +343,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 256918 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 197081 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2065711500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.232903 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_accesses 256917 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.809098 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.738523 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 197080 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2063108500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.232904 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1879254000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232903 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876353000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232904 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 219092 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 186176 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1131972500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.150238 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32916 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1021003500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150238 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32916 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 423151 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 423151 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5261.194030 # average number of cycles each access was blocked
system.cpu.l2cache.ReadReq_accesses 218939 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34396.642358 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.006381 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 186029 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1131993500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.150316 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32910 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020835500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150316 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32910 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 423042 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 423042 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5257.142857 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 5.283534 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 67 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 5.281796 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 352500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 368000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 476010 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34475.262256 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 383257 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3197684000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.194855 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 92753 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 475856 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34449.653358 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 383109 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3195102000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.194906 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 92747 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2900257500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.194855 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 92753 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2897188500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.194906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 92747 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.052815 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.488399 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1730.637326 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16003.856484 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 476010 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34475.262256 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.052860 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.487907 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1732.123670 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15987.736166 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 475856 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34449.653358 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 383257 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3197684000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.194855 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 92753 # number of overall misses
system.cpu.l2cache.overall_hits 383109 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3195102000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.194906 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 92747 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2900257500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.194855 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 92753 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2897188500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.194906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 92747 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 74446 # number of replacements
system.cpu.l2cache.sampled_refs 90349 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 74441 # number of replacements
system.cpu.l2cache.sampled_refs 90342 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17734.493810 # Cycle average of tags in use
system.cpu.l2cache.total_refs 477362 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17719.859836 # Cycle average of tags in use
system.cpu.l2cache.total_refs 477168 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 59324 # number of writebacks
system.cpu.memDep0.conflictingLoads 22261692 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 15435128 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 126939472 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 43126164 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 330753974 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 12738848 # Number of cycles rename is blocking
system.cpu.l2cache.writebacks 59318 # number of writebacks
system.cpu.memDep0.conflictingLoads 17165638 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 325559560 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 34708853 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 151708807 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 618719 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 896183749 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 680208714 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 518824645 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 115765657 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 9844039 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 40602289 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 54969756 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 696 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 79641546 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.timesIdled 3516 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 149957875 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 662477 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 118 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 894828905 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 679288968 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 518109497 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 115552585 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed
system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

3
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

11
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,10 +7,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 02:36:02
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:31:02
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -44,3 +46,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 300930958000 because target called exit()

10
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1810362 # Simulator instruction rate (inst/s)
host_mem_usage 184036 # Number of bytes of host memory used
host_seconds 332.45 # Real time elapsed on the host
host_tick_rate 905187706 # Simulator tick rate (ticks/s)
host_inst_rate 6224890 # Simulator instruction rate (inst/s)
host_mem_usage 232016 # Number of bytes of host memory used
host_seconds 96.69 # Real time elapsed on the host
host_tick_rate 3112463113 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated
@ -44,7 +44,7 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154866966 # Number of memory references
system.cpu.num_refs 153970296 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:13:16
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:44:32
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1603392 # Simulator instruction rate (inst/s)
host_mem_usage 192888 # Number of bytes of host memory used
host_seconds 375.37 # Real time elapsed on the host
host_tick_rate 2039675547 # Simulator tick rate (ticks/s)
host_inst_rate 2723974 # Simulator instruction rate (inst/s)
host_mem_usage 239668 # Number of bytes of host memory used
host_seconds 220.95 # Real time elapsed on the host
host_tick_rate 3465167347 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.765623 # Number of seconds simulated
@ -233,7 +233,7 @@ system.cpu.l2cache.writebacks 59341 # nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154866966 # Number of memory references
system.cpu.num_refs 153970296 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/home/stever/m5/m5_system_2.0b3/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -661,7 +661,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -681,7 +681,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -807,7 +807,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

17
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,14 +7,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:17:04
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
M5 compiled Nov 2 2010 23:00:12
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 23:04:53
M5 executing on aus-bc2-b15
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 118370500
Exiting @ tick 1900828642500 because m5_exit instruction encountered
Exiting @ tick 1900844230500 because m5_exit instruction encountered

1782
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/home/stever/m5/m5_system_2.0b3/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -356,7 +356,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -376,7 +376,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -502,7 +502,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

17
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simout
Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,13 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:17:56
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
M5 compiled Nov 2 2010 23:00:12
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 23:00:25
M5 executing on aus-bc2-b15
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1865720303500 because m5_exit instruction encountered
Exiting @ tick 1866702027500 because m5_exit instruction encountered

979
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

14
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,15 +7,15 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:52
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:32:27
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
Exiting @ tick 134780256500 because target called exit()
Exiting @ tick 136326909500 because target called exit()

590
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 209084 # Simulator instruction rate (inst/s)
host_mem_usage 200220 # Number of bytes of host memory used
host_seconds 1796.28 # Real time elapsed on the host
host_tick_rate 75032789 # Simulator tick rate (ticks/s)
host_inst_rate 228388 # Simulator instruction rate (inst/s)
host_mem_usage 246968 # Number of bytes of host memory used
host_seconds 1644.46 # Real time elapsed on the host
host_tick_rate 82900633 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.134780 # Number of seconds simulated
sim_ticks 134780256500 # Number of ticks simulated
sim_seconds 0.136327 # Number of seconds simulated
sim_ticks 136326909500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 34013245 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 43763729 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1420 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5537198 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 35178330 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 62077463 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 12488414 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 35459307 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 43810174 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1426 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5614078 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 35351284 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 62456368 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 12662154 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 44587532 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 13095097 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 12699878 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 254238271 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.568075 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.238705 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 256761438 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.552665 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.229770 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 122261214 48.09% 48.09% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 50419868 19.83% 67.92% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 19851999 7.81% 75.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 19999442 7.87% 83.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10886968 4.28% 87.88% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 9291241 3.65% 91.53% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5249545 2.06% 93.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 3182897 1.25% 94.85% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 13095097 5.15% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 124458766 48.47% 48.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 50855968 19.81% 68.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 19650568 7.65% 75.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 20252396 7.89% 83.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10775172 4.20% 88.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8940653 3.48% 91.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5548934 2.16% 93.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 3579103 1.39% 95.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 12699878 4.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 254238271 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle
system.cpu.commit.COM:count 398664594 # Number of instructions committed
system.cpu.commit.COM:loads 100651995 # Number of loads committed
system.cpu.commit.COM:loads 94754489 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
system.cpu.commit.COM:refs 168275218 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5532855 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 5609735 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 94873241 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 98058240 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
system.cpu.cpi 0.717728 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.717728 # CPI: Total CPI of All Threads
system.cpu.cpi 0.725964 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.725964 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 95565604 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33374.015748 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31987.257900 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 95563953 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 55100500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_accesses 96258234 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33424.104432 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31993.883792 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96256587 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 55049500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1651 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 670 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 31379500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 1647 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 666 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 31386000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30116.133558 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35471.048513 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73502909 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 536669500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 30170.708432 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35486.697966 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73502915 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 537461000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 17820 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 14625 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 113330000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 17814 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 14619 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 113380000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40485.360393 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40651.222462 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 169086333 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30392.378409 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency
system.cpu.dcache.demand_hits 169066862 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 591770000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_accesses 169778963 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30446.045938 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34666.187739 # average overall mshr miss latency
system.cpu.dcache.demand_hits 169759502 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 592510500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000115 # miss rate for demand accesses
system.cpu.dcache.demand_misses 19471 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 15295 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 144709500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_misses 19461 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 15285 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 144766000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.804225 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3294.106020 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 169086333 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30392.378409 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.804250 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3294.209288 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 169778963 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30446.045938 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34666.187739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 169066862 # number of overall hits
system.cpu.dcache.overall_miss_latency 591770000 # number of overall miss cycles
system.cpu.dcache.overall_hits 169759502 # number of overall hits
system.cpu.dcache.overall_miss_latency 592510500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000115 # miss rate for overall accesses
system.cpu.dcache.overall_misses 19471 # number of overall misses
system.cpu.dcache.overall_mshr_hits 15295 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 144709500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_misses 19461 # number of overall misses
system.cpu.dcache.overall_mshr_hits 15285 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 144766000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -114,227 +114,227 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 781 # number of replacements
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3294.106020 # Cycle average of tags in use
system.cpu.dcache.total_refs 169066865 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3294.209288 # Cycle average of tags in use
system.cpu.dcache.total_refs 169759505 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 662 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 22152007 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4419 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 11286796 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 532040738 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 132274950 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 98625859 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15181213 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 13245 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1185455 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 184734537 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 184683089 # DTB hits
system.cpu.dtb.data_misses 51448 # DTB misses
system.cpu.decode.DECODE:BlockedCycles 21274693 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4421 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 11335478 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 536362282 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 133648516 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 100614513 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15751437 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 13226 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1223716 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 185361756 # DTB accesses
system.cpu.dtb.data_acv 1 # DTB access violations
system.cpu.dtb.data_hits 185333824 # DTB hits
system.cpu.dtb.data_misses 27932 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 104442295 # DTB read accesses
system.cpu.dtb.read_accesses 105061264 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 104392308 # DTB read hits
system.cpu.dtb.read_misses 49987 # DTB read misses
system.cpu.dtb.write_accesses 80292242 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 80290781 # DTB write hits
system.cpu.dtb.write_misses 1461 # DTB write misses
system.cpu.fetch.Branches 62077463 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 63755206 # Number of cache lines fetched
system.cpu.fetch.Cycles 165857748 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1527822 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 544006695 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 5884776 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.230291 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 63755206 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 46501659 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.018125 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 269419484 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.019181 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.021968 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.read_hits 105034802 # DTB read hits
system.cpu.dtb.read_misses 26462 # DTB read misses
system.cpu.dtb.write_accesses 80300492 # DTB write accesses
system.cpu.dtb.write_acv 1 # DTB write access violations
system.cpu.dtb.write_hits 80299022 # DTB write hits
system.cpu.dtb.write_misses 1470 # DTB write misses
system.cpu.fetch.Branches 62456368 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 64427463 # Number of cache lines fetched
system.cpu.fetch.Cycles 168595579 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1484985 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 548969588 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6021463 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.229068 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 64427463 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 48121461 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.013431 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 272512875 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.014472 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.018403 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 167317249 62.10% 62.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9830332 3.65% 65.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10264297 3.81% 69.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 7467850 2.77% 72.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 14528793 5.39% 77.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9632139 3.58% 81.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7095921 2.63% 83.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3870398 1.44% 85.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39412505 14.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 168345063 61.78% 61.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 11153110 4.09% 65.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 11633749 4.27% 70.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6179991 2.27% 72.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 14406846 5.29% 77.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9876694 3.62% 81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7175383 2.63% 83.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3990457 1.46% 85.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39751582 14.59% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 269419484 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 63755206 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32282.788581 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30880.348450 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 63750372 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 156055000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4834 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 931 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120526000 # number of ReadReq MSHR miss cycles
system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 64422617 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 156225500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000075 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4846 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 935 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120601500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3903 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 3911 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 16333.684858 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 16472.159806 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 63755206 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32282.788581 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency
system.cpu.icache.demand_hits 63750372 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 156055000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
system.cpu.icache.demand_misses 4834 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 931 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120526000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_accesses 64427463 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32238.031366 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30836.486832 # average overall mshr miss latency
system.cpu.icache.demand_hits 64422617 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 156225500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000075 # miss rate for demand accesses
system.cpu.icache.demand_misses 4846 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 935 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120601500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 3911 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.891530 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1825.852920 # Average occupied blocks per context
system.cpu.icache.overall_accesses 63755206 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32282.788581 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.891874 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1826.557172 # Average occupied blocks per context
system.cpu.icache.overall_accesses 64427463 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32238.031366 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30836.486832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 63750372 # number of overall hits
system.cpu.icache.overall_miss_latency 156055000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
system.cpu.icache.overall_misses 4834 # number of overall misses
system.cpu.icache.overall_mshr_hits 931 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120526000 # number of overall MSHR miss cycles
system.cpu.icache.overall_hits 64422617 # number of overall hits
system.cpu.icache.overall_miss_latency 156225500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000075 # miss rate for overall accesses
system.cpu.icache.overall_misses 4846 # number of overall misses
system.cpu.icache.overall_mshr_hits 935 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120601500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 3911 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1981 # number of replacements
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
system.cpu.icache.replacements 1989 # number of replacements
system.cpu.icache.sampled_refs 3911 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1825.852920 # Cycle average of tags in use
system.cpu.icache.total_refs 63750372 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1826.557172 # Cycle average of tags in use
system.cpu.icache.total_refs 64422617 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 141032 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 50928648 # Number of branches executed
system.cpu.iew.EXEC:nop 27198310 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.554098 # Inst execution rate
system.cpu.iew.EXEC:refs 191466035 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 80302922 # Number of stores executed
system.cpu.idleCycles 140947 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 51277692 # Number of branches executed
system.cpu.iew.EXEC:nop 27475837 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.546858 # Inst execution rate
system.cpu.iew.EXEC:refs 185361805 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 80300524 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 288648946 # num instructions consuming a value
system.cpu.iew.WB:count 415155943 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.699341 # average fanout of values written-back
system.cpu.iew.WB:consumers 290508552 # num instructions consuming a value
system.cpu.iew.WB:count 417530576 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.697486 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 201863998 # num instructions producing a value
system.cpu.iew.WB:rate 1.540121 # insts written-back per cycle
system.cpu.iew.WB:sent 415846665 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6072161 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3214599 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 125039862 # Number of dispatched load instructions
system.cpu.iew.WB:producers 202625525 # num instructions producing a value
system.cpu.iew.WB:rate 1.531358 # insts written-back per cycle
system.cpu.iew.WB:sent 418298724 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6117740 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3299737 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 117580442 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6489838 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 92505583 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 493538259 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 111163113 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8697897 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 418923368 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 138014 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewDispSquashedInsts 6436127 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 92914841 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 496723261 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 105061281 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8627247 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 421756759 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 169659 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 28455 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15181213 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 561595 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 28133 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15751437 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 607162 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 8650010 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 47350 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 8600585 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 30861 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 540044 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 176691 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 24387867 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 18974181 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 540044 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1086448 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4985713 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.393286 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.393286 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 663165 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 175980 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 22825953 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 19394112 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 166094034 38.84% 38.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2150895 0.50% 39.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34767843 8.13% 47.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7837636 1.83% 49.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2956341 0.69% 50.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16811834 3.93% 53.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571362 0.37% 54.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 113187864 26.47% 80.78% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82209875 19.22% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 175581687 40.80% 40.80% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2149994 0.50% 41.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34727338 8.07% 49.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7823215 1.82% 51.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2961066 0.69% 51.88% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16836878 3.91% 55.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569908 0.36% 56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 106389727 24.72% 80.88% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82310612 19.12% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 427621265 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 9425623 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.022042 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 430384006 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 8629906 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.020052 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 22465 0.24% 0.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 44257 0.47% 0.71% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 507 0.01% 0.71% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 7079 0.08% 0.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 1310742 13.91% 14.69% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 1081807 11.48% 26.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5661778 60.07% 86.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1296988 13.76% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 24317 0.28% 0.28% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.28% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.28% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 44159 0.51% 0.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 3134 0.04% 0.83% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 6690 0.08% 0.91% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 1184776 13.73% 14.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 981942 11.38% 26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5222594 60.52% 86.53% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1162294 13.47% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 269419484 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.587195 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.714658 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 272512875 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.579316 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717067 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 98807587 36.67% 36.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 58261038 21.62% 58.30% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 40917124 15.19% 73.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 29020181 10.77% 84.26% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 23205890 8.61% 92.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 11236315 4.17% 97.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5001720 1.86% 98.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 2307051 0.86% 99.75% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 662578 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 101003308 37.06% 37.06% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 58496079 21.47% 58.53% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 41698303 15.30% 73.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 27977806 10.27% 84.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 23760656 8.72% 92.82% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 11524865 4.23% 97.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5162499 1.89% 98.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 2198912 0.81% 99.75% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 690447 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 269419484 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.586365 # Inst issue rate
system.cpu.iq.iqInstsAdded 466339708 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 427621265 # Number of instructions issued
system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate
system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 89739850 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 704910 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 92662056 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 866219 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 69710487 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedOperandsExamined 70475093 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 63755513 # ITB accesses
system.cpu.itb.fetch_accesses 64427767 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 63755206 # ITB hits
system.cpu.itb.fetch_misses 307 # ITB misses
system.cpu.itb.fetch_hits 64427463 # ITB hits
system.cpu.itb.fetch_misses 304 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -344,97 +344,97 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34585.272553 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31456.646478 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34601.370736 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.240357 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 108494000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 108544500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.980619 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98679500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98684500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980619 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4880 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.396450 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.467456 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 145160000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.865779 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4225 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 131691000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865779 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4225 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4888 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.345635 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.742134 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 661 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 145228500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.864771 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4227 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 131754500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864771 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4227 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.152443 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.153637 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 8079 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34454.496061 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 253654000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.911251 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7362 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 8087 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34461.298207 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31292.639870 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 723 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 253773000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.910597 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7364 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 230370500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.911251 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7362 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 230439000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.910597 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7364 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.108627 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011574 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3559.477751 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 379.255991 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 8079 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34454.496061 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.108677 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011575 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3561.129355 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 379.284506 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 8087 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34461.298207 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31292.639870 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 717 # number of overall hits
system.cpu.l2cache.overall_miss_latency 253654000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.911251 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7362 # number of overall misses
system.cpu.l2cache.overall_hits 723 # number of overall hits
system.cpu.l2cache.overall_miss_latency 253773000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.910597 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7364 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 230370500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.911251 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7362 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 230439000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.910597 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7364 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 13 # number of replacements
system.cpu.l2cache.sampled_refs 4769 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 4771 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3938.733742 # Cycle average of tags in use
system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3940.413861 # Cycle average of tags in use
system.cpu.l2cache.total_refs 733 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 72822522 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 52763057 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 125039862 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 92505583 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 269560516 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 11010620 # Number of cycles rename is blocking
system.cpu.memDep0.conflictingLoads 71937561 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 272653822 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2256823 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 137290050 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 7674469 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 138476212 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 7076079 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 683176131 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 518444566 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 335488186 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 94400681 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15181213 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 11169785 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 75955845 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 367135 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37569 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 24308277 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 261 # count of temporary serializing insts renamed
system.cpu.timesIdled 3095 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:RenameLookups 688559814 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 522801702 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 337940166 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 96677987 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed
system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

3
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
View file

@ -46,3 +46,6 @@ Writing to chair.cook.ppm
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

11
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,10 +7,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 02:33:35
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:31:02
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -16,3 +18,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.183333
Exiting @ tick 199332411500 because target called exit()

10
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1825585 # Simulator instruction rate (inst/s)
host_mem_usage 190564 # Number of bytes of host memory used
host_seconds 218.38 # Real time elapsed on the host
host_tick_rate 912792158 # Simulator tick rate (ticks/s)
host_inst_rate 4732897 # Simulator instruction rate (inst/s)
host_mem_usage 238480 # Number of bytes of host memory used
host_seconds 84.23 # Real time elapsed on the host
host_tick_rate 2366444186 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
@ -44,7 +44,7 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.num_insts 398664595 # Number of instructions executed
system.cpu.num_refs 174183453 # Number of memory references
system.cpu.num_refs 168275274 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

12
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:42:55
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:41:16
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1240949 # Simulator instruction rate (inst/s)
host_mem_usage 199424 # Number of bytes of host memory used
host_seconds 321.26 # Real time elapsed on the host
host_tick_rate 1766004728 # Simulator tick rate (ticks/s)
host_inst_rate 2252516 # Simulator instruction rate (inst/s)
host_mem_usage 246196 # Number of bytes of host memory used
host_seconds 176.99 # Real time elapsed on the host
host_tick_rate 3205571054 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567343 # Number of seconds simulated
@ -233,7 +233,7 @@ system.cpu.l2cache.writebacks 0 # nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1134686340 # number of cpu cycles simulated
system.cpu.num_insts 398664609 # Number of instructions executed
system.cpu.num_refs 174183455 # Number of memory references
system.cpu.num_refs 168275276 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

14
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:48:50
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:48:16
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -1390,4 +1392,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 702197148500 because target called exit()
Exiting @ tick 699853545500 because target called exit()

616
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,295 +1,295 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 211797 # Simulator instruction rate (inst/s)
host_mem_usage 200548 # Number of bytes of host memory used
host_seconds 8607.50 # Real time elapsed on the host
host_tick_rate 81579716 # Simulator tick rate (ticks/s)
host_inst_rate 223208 # Simulator instruction rate (inst/s)
host_mem_usage 247308 # Number of bytes of host memory used
host_seconds 8167.46 # Real time elapsed on the host
host_tick_rate 85688066 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.702197 # Number of seconds simulated
sim_ticks 702197148500 # Number of ticks simulated
sim_seconds 0.699854 # Number of seconds simulated
sim_ticks 699853545500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 239361289 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 292350506 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 817 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 28355767 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 232672074 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 346972918 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 49326443 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 236956975 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 289938750 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 831 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 28355381 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 231810934 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 346110000 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 49326422 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 266706457 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 67076252 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 69159882 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1304193061 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.540407 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.191824 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1301001982 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.544185 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.202693 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 594441372 45.58% 45.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 274309752 21.03% 66.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 176336103 13.52% 80.13% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 68165188 5.23% 85.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 46116026 3.54% 88.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 34003883 2.61% 91.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 19794848 1.52% 93.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 23949637 1.84% 94.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 67076252 5.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 594587557 45.70% 45.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 273537466 21.03% 66.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 173768132 13.36% 80.08% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 65535935 5.04% 85.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 48802734 3.75% 88.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 34016841 2.61% 91.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 18422173 1.42% 92.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 23171262 1.78% 94.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 69159882 5.32% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1304193061 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1301001982 # Number of insts commited each cycle
system.cpu.commit.COM:count 2008987604 # Number of instructions committed
system.cpu.commit.COM:loads 511595302 # Number of loads committed
system.cpu.commit.COM:loads 511070026 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 722390433 # Number of memory references committed
system.cpu.commit.COM:refs 721864922 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 28343948 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 28343547 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 694286197 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 686655102 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.770357 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.770357 # CPI: Total CPI of All Threads
system.cpu.cpi 0.767786 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.767786 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 463422916 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37046.413098 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34119.469160 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 461494441 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 71443081500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004161 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1928475 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 469203 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 49789586000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_accesses 463432344 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37080.555893 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34168.158766 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 461506110 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 71425827500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004156 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1926234 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 467104 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 49855785500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1459272 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 1459130 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 37873.224315 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34361.981856 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210247567 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 20729113991 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 37974.555169 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34786.244627 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210247535 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 20785790492 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 547329 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 475679 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2462036000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 547361 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 475709 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2492504000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71650 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6041.666667 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_misses 71652 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6045.454545 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 438.782653 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.dcache.avg_refs 438.830385 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 72500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 66500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 674217812 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 37229.197259 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency
system.cpu.dcache.demand_hits 671742008 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 92172195491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003672 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2475804 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 944882 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 52251622000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002271 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530922 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 674227240 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 37278.381462 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34197.089788 # average overall mshr miss latency
system.cpu.dcache.demand_hits 671753645 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 92211617992 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003669 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2473595 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 942813 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 52348289500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002270 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530782 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.103693 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 674217812 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37229.197259 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 4095.102160 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 674227240 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37278.381462 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34197.089788 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 671742008 # number of overall hits
system.cpu.dcache.overall_miss_latency 92172195491 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003672 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2475804 # number of overall misses
system.cpu.dcache.overall_mshr_hits 944882 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 52251622000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002271 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530922 # number of overall MSHR misses
system.cpu.dcache.overall_hits 671753645 # number of overall hits
system.cpu.dcache.overall_miss_latency 92211617992 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003669 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2473595 # number of overall misses
system.cpu.dcache.overall_mshr_hits 942813 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 52348289500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002270 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530782 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1526826 # number of replacements
system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 1526686 # number of replacements
system.cpu.dcache.sampled_refs 1530782 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.103693 # Cycle average of tags in use
system.cpu.dcache.total_refs 671742017 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107349 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 30546765 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 11879 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 30415983 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2934070840 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 711662273 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 561899990 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 100055757 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45705 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 84033 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 772892535 # DTB accesses
system.cpu.dcache.tagsinuse 4095.102160 # Cycle average of tags in use
system.cpu.dcache.total_refs 671753654 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 273600000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107376 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 31383327 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 11899 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 30414248 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2922892540 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 711748047 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 557786525 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 98570758 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45781 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 84083 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 772896747 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 772261224 # DTB hits
system.cpu.dtb.data_misses 631311 # DTB misses
system.cpu.dtb.data_hits 772274639 # DTB hits
system.cpu.dtb.data_misses 622108 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 514571381 # DTB read accesses
system.cpu.dtb.read_accesses 514573141 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 513977951 # DTB read hits
system.cpu.dtb.read_misses 593430 # DTB read misses
system.cpu.dtb.write_accesses 258321154 # DTB write accesses
system.cpu.dtb.read_hits 513988912 # DTB read hits
system.cpu.dtb.read_misses 584229 # DTB read misses
system.cpu.dtb.write_accesses 258323606 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 258283273 # DTB write hits
system.cpu.dtb.write_misses 37881 # DTB write misses
system.cpu.fetch.Branches 346972918 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 347200626 # Number of cache lines fetched
system.cpu.fetch.Cycles 925414333 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 4548226 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3016464690 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28792576 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.247062 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 347200626 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 288687732 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.147876 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1404248818 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.148098 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.027750 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 258285727 # DTB write hits
system.cpu.dtb.write_misses 37879 # DTB write misses
system.cpu.fetch.Branches 346110000 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 346350693 # Number of cache lines fetched
system.cpu.fetch.Cycles 922065710 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 4322310 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3016744002 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28792194 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.247273 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 346350693 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 286283397 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.155268 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1399572740 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.155475 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.033799 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 826035319 58.82% 58.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 54061013 3.85% 62.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 40121660 2.86% 65.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 63576700 4.53% 70.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 121382183 8.64% 78.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 34599008 2.46% 81.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 37926839 2.70% 83.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7023317 0.50% 84.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 219522779 15.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 823857927 58.86% 58.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 53203147 3.80% 62.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38576379 2.76% 65.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 62027989 4.43% 69.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 120526716 8.61% 78.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 36144136 2.58% 81.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38696119 2.76% 83.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7022744 0.50% 84.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 219517583 15.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1404248818 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 347200626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15854.453498 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.008587 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 347189949 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 169278000 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 1399572740 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 346350693 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15859.786377 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.165644 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 346340020 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 169271500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10677 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 895 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 113843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 10673 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 893 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 113899500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 9782 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 9780 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 35496.365300 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 35416.711320 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 347200626 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15854.453498 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency
system.cpu.icache.demand_hits 347189949 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 169278000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 346350693 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15859.786377 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11646.165644 # average overall mshr miss latency
system.cpu.icache.demand_hits 346340020 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 169271500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
system.cpu.icache.demand_misses 10677 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 895 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 113843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 10673 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 893 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 113899500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 9782 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 9780 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.787157 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1612.097956 # Average occupied blocks per context
system.cpu.icache.overall_accesses 347200626 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15854.453498 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.787644 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1613.094407 # Average occupied blocks per context
system.cpu.icache.overall_accesses 346350693 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15859.786377 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11646.165644 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 347189949 # number of overall hits
system.cpu.icache.overall_miss_latency 169278000 # number of overall miss cycles
system.cpu.icache.overall_hits 346340020 # number of overall hits
system.cpu.icache.overall_miss_latency 169271500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
system.cpu.icache.overall_misses 10677 # number of overall misses
system.cpu.icache.overall_mshr_hits 895 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 113843000 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 10673 # number of overall misses
system.cpu.icache.overall_mshr_hits 893 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 113899500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 9782 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 9780 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 8111 # number of replacements
system.cpu.icache.sampled_refs 9781 # Sample count of references to valid blocks.
system.cpu.icache.replacements 8107 # number of replacements
system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1612.097956 # Cycle average of tags in use
system.cpu.icache.total_refs 347189949 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1613.094407 # Cycle average of tags in use
system.cpu.icache.total_refs 346340020 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 145480 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 274684945 # Number of branches executed
system.cpu.iew.EXEC:nop 329038670 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.425383 # Inst execution rate
system.cpu.iew.EXEC:refs 773428063 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 258322146 # Number of stores executed
system.cpu.idleCycles 134352 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 273830635 # Number of branches executed
system.cpu.iew.EXEC:nop 328407505 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.428327 # Inst execution rate
system.cpu.iew.EXEC:refs 772897467 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 258324248 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1632528882 # num instructions consuming a value
system.cpu.iew.WB:count 2000778402 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.695828 # average fanout of values written-back
system.cpu.iew.WB:consumers 1628729095 # num instructions consuming a value
system.cpu.iew.WB:count 1998228085 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.696311 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1135959868 # num instructions producing a value
system.cpu.iew.WB:rate 1.424656 # insts written-back per cycle
system.cpu.iew.WB:sent 2001740023 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 30875630 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3371474 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 655915316 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 69 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 46568 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302840686 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2713549765 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 515105917 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 84189444 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2001799378 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 130178 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1134102180 # num instructions producing a value
system.cpu.iew.WB:rate 1.427604 # insts written-back per cycle
system.cpu.iew.WB:sent 1999182270 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 30874102 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3363341 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 651766159 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 47334 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302842543 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2705917270 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 514573219 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 84025502 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1999238951 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 131775 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1349 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 100055757 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 139189 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 2470 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 98570758 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 141708 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 50550937 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 225 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 50552549 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 226 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3543 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 4083 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 144320014 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 92045555 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3543 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 788016 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 30087614 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.298099 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.298099 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 3569 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 4004 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 140696133 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 92047647 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3569 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 787992 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 30086110 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.302446 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.302446 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203839026 57.71% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1202273174 57.71% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 18400 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850839 1.34% 59.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254698 0.40% 59.44% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204647 0.35% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850829 1.34% 59.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.45% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 555691648 26.64% 86.43% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283126808 13.57% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 554531536 26.62% 86.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283128420 13.59% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2085988822 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 36673966 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017581 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 2083264453 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 36972943 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017748 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5496 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5487 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # at
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 27909398 76.10% 76.12% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 8759072 23.88% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 27783755 75.15% 75.16% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 9183701 24.84% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1404248818 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.485484 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.638010 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1399572740 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.488500 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636855 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 532242124 37.90% 37.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 283422756 20.18% 58.09% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 275702525 19.63% 77.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 156569721 11.15% 88.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 62891882 4.48% 93.35% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 46986104 3.35% 96.69% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 33054153 2.35% 99.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10407537 0.74% 99.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 2972016 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 529155150 37.81% 37.81% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 284031316 20.29% 58.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 272535453 19.47% 77.58% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 155737122 11.13% 88.70% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 63080149 4.51% 93.21% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 50551840 3.61% 96.82% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 32415692 2.32% 99.14% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 9151227 0.65% 99.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 2914791 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1404248818 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.485330 # Inst issue rate
system.cpu.iq.iqInstsAdded 2384511026 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2085988822 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 561440182 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12400568 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 517571269 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 1399572740 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.488357 # Inst issue rate
system.cpu.iq.iqInstsAdded 2377509698 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2083264453 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 554439445 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12400290 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 512014253 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 347200834 # ITB accesses
system.cpu.itb.fetch_accesses 346350897 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 347200626 # ITB hits
system.cpu.itb.fetch_misses 208 # ITB misses
system.cpu.itb.fetch_hits 346350693 # ITB hits
system.cpu.itb.fetch_misses 204 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -343,98 +343,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 35152.205453 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32141.578294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_accesses 71652 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.301769 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32133.325356 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2350171000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.933105 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 66857 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148889500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933105 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 66857 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1469054 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34210.498210 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.429333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 55232 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 48367555000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.962403 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1413822 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43829089000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962403 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1413822 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107349 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107349 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_miss_latency 2349178000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.933107 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 66859 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148402000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933107 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 66859 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1468910 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34259.233914 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.653566 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 55127 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 48435122500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.962471 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1413783 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43828197000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962471 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1413783 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107376 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107376 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.041538 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 0.041462 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540704 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34253.019054 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 60025 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 50717726000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.961041 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1480679 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 1540562 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34298.838274 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.799827 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 59920 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 50784300500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.961105 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1480642 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 45977978500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.961041 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1480679 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 45976599000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.961105 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1480642 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.881669 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.093123 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 28890.531626 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3051.454384 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540704 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34253.019054 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.881690 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.093104 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 28891.219129 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3050.823306 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540562 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34298.838274 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.799827 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 60025 # number of overall hits
system.cpu.l2cache.overall_miss_latency 50717726000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.961041 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1480679 # number of overall misses
system.cpu.l2cache.overall_hits 59920 # number of overall hits
system.cpu.l2cache.overall_miss_latency 50784300500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.961105 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1480642 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 45977978500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.961041 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1480679 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 45976599000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.961105 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1480642 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 1480409 # number of replacements
system.cpu.l2cache.sampled_refs 1513096 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 1480407 # number of replacements
system.cpu.l2cache.sampled_refs 1513094 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31941.986010 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62851 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 31942.042436 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62736 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66898 # number of writebacks
system.cpu.memDep0.conflictingLoads 122494554 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20280761 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 655915316 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 302840686 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1404394298 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 19598244 # Number of cycles rename is blocking
system.cpu.memDep0.conflictingLoads 118268475 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 21018090 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 651766159 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 302842543 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1399707092 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 19659094 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 671773 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 725577995 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10516920 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 17 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3307285723 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2838114179 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1889955714 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 546658925 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 100055757 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 12336225 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 504986644 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 21672 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2827 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 26425102 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 76 # count of temporary serializing insts renamed
system.cpu.timesIdled 3680 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 672257 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 725352464 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10949822 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3294686946 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2827218564 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1880762420 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 542782008 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 98570758 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 13186877 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 495793350 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 21539 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2826 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 26818332 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed
system.cpu.timesIdled 3665 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

3
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
View file

@ -2,3 +2,6 @@ warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,10 +7,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:10:59
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:59:54
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -1390,3 +1392,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 1004710587000 because target called exit()

10
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2073139 # Simulator instruction rate (inst/s)
host_mem_usage 190360 # Number of bytes of host memory used
host_seconds 969.06 # Real time elapsed on the host
host_tick_rate 1036792835 # Simulator tick rate (ticks/s)
host_inst_rate 5515431 # Simulator instruction rate (inst/s)
host_mem_usage 238276 # Number of bytes of host memory used
host_seconds 364.25 # Real time elapsed on the host
host_tick_rate 2758309260 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated
@ -44,7 +44,7 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
system.cpu.num_insts 2008987605 # Number of instructions executed
system.cpu.num_refs 722823898 # Number of memory references
system.cpu.num_refs 722298387 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

12
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:48:17
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:06:01
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1340007 # Simulator instruction rate (inst/s)
host_mem_usage 199308 # Number of bytes of host memory used
host_seconds 1499.24 # Real time elapsed on the host
host_tick_rate 1876600376 # Simulator tick rate (ticks/s)
host_inst_rate 2134538 # Simulator instruction rate (inst/s)
host_mem_usage 246068 # Number of bytes of host memory used
host_seconds 941.18 # Real time elapsed on the host
host_tick_rate 2989292617 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.813468 # Number of seconds simulated
@ -233,7 +233,7 @@ system.cpu.l2cache.writebacks 66898 # nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
system.cpu.num_insts 2008987605 # Number of instructions executed
system.cpu.num_refs 722823898 # Number of memory references
system.cpu.num_refs 722298387 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -186,12 +186,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

4
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr
View file

@ -1,9 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetching currently unimplemented
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

12
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:19:32
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:06:02
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

24
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 58405 # Simulator instruction rate (inst/s)
host_mem_usage 209896 # Number of bytes of host memory used
host_seconds 1512.56 # Real time elapsed on the host
host_tick_rate 68868083 # Simulator tick rate (ticks/s)
host_inst_rate 67514 # Simulator instruction rate (inst/s)
host_mem_usage 256704 # Number of bytes of host memory used
host_seconds 1308.48 # Real time elapsed on the host
host_tick_rate 79609109 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.104167 # Number of seconds simulated
sim_ticks 104166942500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations
system.cpu.AGEN-Unit.agens 34890015 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups 11507768 # Number of BTB lookups
@ -19,7 +19,7 @@ system.cpu.Branch-Predictor.lookups 13754477 # Nu
system.cpu.Branch-Predictor.predictedNotTaken 5723290 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 8031187 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 1659774 # Number of times the RAS was used to get a target.
system.cpu.Execution-Unit.executions 53075554 # Number of Instructions Executed.
system.cpu.Execution-Unit.executions 53409557 # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct 4.741700 # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted 652196 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 13102281 # Number of Branches Incorrectly Predicted
@ -34,11 +34,11 @@ system.cpu.RegFile-Manager.regForwards 2135966 # Nu
system.cpu.activity 85.354290 # Percentage of cycles cpu is active
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.comInts 30457224 # Number of Integer instructions committed
system.cpu.comLoads 20379399 # Number of Load instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comNops 8748916 # Number of Nop instructions committed
system.cpu.comStores 14844619 # Number of Store instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
@ -284,9 +284,9 @@ system.cpu.stage-1.utilization 42.414607 # Pe
system.cpu.stage-2.idleCycles 118518100 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 43.111463 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 173102616 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 16.910965 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 173436619 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 34897267 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 16.750644 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 119993213 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization 42.403411 # Percentage of cycles stage was utilized (processing insts).

4
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

14
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,12 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:41:46
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:35:53
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 27033689000 because target called exit()
Exiting @ tick 26961586000 because target called exit()

636
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,340 +1,340 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 221900 # Simulator instruction rate (inst/s)
host_mem_usage 202972 # Number of bytes of host memory used
host_seconds 358.68 # Real time elapsed on the host
host_tick_rate 75369122 # Simulator tick rate (ticks/s)
host_inst_rate 245514 # Simulator instruction rate (inst/s)
host_mem_usage 249732 # Number of bytes of host memory used
host_seconds 324.18 # Real time elapsed on the host
host_tick_rate 83167459 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027034 # Number of seconds simulated
sim_ticks 27033689000 # Number of ticks simulated
sim_seconds 0.026962 # Number of seconds simulated
sim_ticks 26961586000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 8073345 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 14152511 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 36189 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 458905 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 10574319 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 16281513 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1942543 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 8073497 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 14157572 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 36043 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 458661 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 10575039 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 16280778 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1941652 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3315405 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 3390195 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 51596234 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.712153 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.330354 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 51426557 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.717803 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.342707 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 22410479 43.43% 43.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 11292136 21.89% 65.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5122096 9.93% 75.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3547417 6.88% 82.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2566622 4.97% 87.10% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1508057 2.92% 90.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1006074 1.95% 91.97% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 827948 1.60% 93.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 3315405 6.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 22406480 43.57% 43.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 11177974 21.74% 65.31% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5100083 9.92% 75.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3515976 6.84% 82.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2514692 4.89% 86.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1504113 2.92% 89.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1005597 1.96% 91.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 811447 1.58% 93.41% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 3390195 6.59% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 51596234 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 51426557 # Number of insts commited each cycle
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:loads 20276638 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:refs 34890015 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 362306 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 362167 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 8339248 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 8347307 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.679309 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.679309 # CPI: Total CPI of All Threads
system.cpu.cpi 0.677497 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.677497 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 20462752 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30131.608065 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20434.335315 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20316340 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4411629000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007155 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 146412 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 84834 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1258305500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61578 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_accesses 20461848 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30161.580175 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20422.684261 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20315611 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4410739000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007147 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 146237 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 84626 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1258262000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61611 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 31003.810080 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32919.803194 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13581378 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 31995900999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.070620 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1031999 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 888502 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 4723892999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009820 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143497 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 32533.052088 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32982.737586 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13581415 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 33572873499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.070618 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1031962 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 888471 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 4732725999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009819 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143491 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 165.294463 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 165.269329 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 35076129 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30895.443100 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33897718 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 36407529999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.033596 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1178411 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 973336 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5982198499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_accesses 35075225 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 32238.707128 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29209.798047 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33897026 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 37983612499 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.033591 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1178199 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 973097 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5990987999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005847 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 205075 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 205102 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995480 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4077.485052 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 35076129 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30895.443100 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.995502 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4077.575152 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 35075225 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32238.707128 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29209.798047 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33897718 # number of overall hits
system.cpu.dcache.overall_miss_latency 36407529999 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.033596 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1178411 # number of overall misses
system.cpu.dcache.overall_mshr_hits 973336 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5982198499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_hits 33897026 # number of overall hits
system.cpu.dcache.overall_miss_latency 37983612499 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.033591 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1178199 # number of overall misses
system.cpu.dcache.overall_mshr_hits 973097 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5990987999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005847 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 205075 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 205102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200979 # number of replacements
system.cpu.dcache.sampled_refs 205075 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 201006 # number of replacements
system.cpu.dcache.sampled_refs 205102 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4077.485052 # Cycle average of tags in use
system.cpu.dcache.total_refs 33897762 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 181365000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161485 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3372983 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97431 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3660168 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 101877731 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 28530714 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 19554245 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1300005 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 281200 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 138292 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 36642762 # DTB accesses
system.cpu.dtb.data_acv 38 # DTB access violations
system.cpu.dtb.data_hits 36466941 # DTB hits
system.cpu.dtb.data_misses 175821 # DTB misses
system.cpu.dcache.tagsinuse 4077.575152 # Cycle average of tags in use
system.cpu.dcache.total_refs 33897070 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 178565000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161507 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3275994 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97418 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3660154 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 101876983 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 28458490 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 19656582 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1300870 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 282338 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 35491 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 36639089 # DTB accesses
system.cpu.dtb.data_acv 39 # DTB access violations
system.cpu.dtb.data_hits 36464202 # DTB hits
system.cpu.dtb.data_misses 174887 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 21568925 # DTB read accesses
system.cpu.dtb.read_accesses 21567895 # DTB read accesses
system.cpu.dtb.read_acv 36 # DTB read access violations
system.cpu.dtb.read_hits 21411469 # DTB read hits
system.cpu.dtb.read_misses 157456 # DTB read misses
system.cpu.dtb.write_accesses 15073837 # DTB write accesses
system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_hits 15055472 # DTB write hits
system.cpu.dtb.write_misses 18365 # DTB write misses
system.cpu.fetch.Branches 16281513 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13394440 # Number of cache lines fetched
system.cpu.fetch.Cycles 33285984 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 153835 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103456008 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 576870 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.301134 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13394440 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 10015888 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.913464 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 52896239 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.955829 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.944816 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.read_hits 21410565 # DTB read hits
system.cpu.dtb.read_misses 157330 # DTB read misses
system.cpu.dtb.write_accesses 15071194 # DTB write accesses
system.cpu.dtb.write_acv 3 # DTB write access violations
system.cpu.dtb.write_hits 15053637 # DTB write hits
system.cpu.dtb.write_misses 17557 # DTB write misses
system.cpu.fetch.Branches 16280778 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13394904 # Number of cache lines fetched
system.cpu.fetch.Cycles 33285903 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 154345 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103458756 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 576280 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.301925 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13394904 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 10015149 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.918633 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 52727427 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.962143 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.947691 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33031612 62.45% 62.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1863332 3.52% 65.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1548849 2.93% 68.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1858475 3.51% 72.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3937136 7.44% 79.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1852242 3.50% 83.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 690247 1.30% 84.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1146451 2.17% 86.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6967895 13.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 32863334 62.33% 62.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1866571 3.54% 65.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1546342 2.93% 68.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1858063 3.52% 72.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3933633 7.46% 79.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1853024 3.51% 83.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 690881 1.31% 84.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1144258 2.17% 86.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6971321 13.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 52896239 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 13394440 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 9549.980865 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6051.228388 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 13305596 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 848458500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006633 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 88844 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 2837 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 520448000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006421 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 86007 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 52727427 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 13394904 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 9553.478677 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6055.148214 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 13306149 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 847919000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006626 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 88755 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 2832 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 520276500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006415 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 85923 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 154.705439 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 154.863120 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 13394440 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 9549.980865 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency
system.cpu.icache.demand_hits 13305596 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 848458500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006633 # miss rate for demand accesses
system.cpu.icache.demand_misses 88844 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 2837 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 520448000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006421 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 86007 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 13394904 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 9553.478677 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6055.148214 # average overall mshr miss latency
system.cpu.icache.demand_hits 13306149 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 847919000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006626 # miss rate for demand accesses
system.cpu.icache.demand_misses 88755 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 2832 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 520276500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006415 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 85923 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.936980 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1918.935161 # Average occupied blocks per context
system.cpu.icache.overall_accesses 13394440 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 9549.980865 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.937341 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1919.673560 # Average occupied blocks per context
system.cpu.icache.overall_accesses 13394904 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 9553.478677 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6055.148214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 13305596 # number of overall hits
system.cpu.icache.overall_miss_latency 848458500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006633 # miss rate for overall accesses
system.cpu.icache.overall_misses 88844 # number of overall misses
system.cpu.icache.overall_mshr_hits 2837 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 520448000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006421 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 86007 # number of overall MSHR misses
system.cpu.icache.overall_hits 13306149 # number of overall hits
system.cpu.icache.overall_miss_latency 847919000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006626 # miss rate for overall accesses
system.cpu.icache.overall_misses 88755 # number of overall misses
system.cpu.icache.overall_mshr_hits 2832 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 520276500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006415 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 85923 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 83959 # number of replacements
system.cpu.icache.sampled_refs 86006 # Sample count of references to valid blocks.
system.cpu.icache.replacements 83875 # number of replacements
system.cpu.icache.sampled_refs 85922 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1918.935161 # Cycle average of tags in use
system.cpu.icache.total_refs 13305596 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1919.673560 # Cycle average of tags in use
system.cpu.icache.total_refs 13306149 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1171140 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14765953 # Number of branches executed
system.cpu.iew.EXEC:nop 9399098 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.570651 # Inst execution rate
system.cpu.iew.EXEC:refs 36985556 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15306955 # Number of stores executed
system.cpu.idleCycles 1195746 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14762410 # Number of branches executed
system.cpu.iew.EXEC:nop 9405310 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.574714 # Inst execution rate
system.cpu.iew.EXEC:refs 36640920 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15071432 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 42195611 # num instructions consuming a value
system.cpu.iew.WB:count 84441959 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765718 # average fanout of values written-back
system.cpu.iew.WB:consumers 42200394 # num instructions consuming a value
system.cpu.iew.WB:count 84434185 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765638 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32309953 # num instructions producing a value
system.cpu.iew.WB:rate 1.561791 # insts written-back per cycle
system.cpu.iew.WB:sent 84679067 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 403539 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 558736 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 23014663 # Number of dispatched load instructions
system.cpu.iew.WB:producers 32310240 # num instructions producing a value
system.cpu.iew.WB:rate 1.565824 # insts written-back per cycle
system.cpu.iew.WB:sent 84670704 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 403347 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 511454 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 22901502 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5005 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 344896 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 16344120 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 99062445 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21678601 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539249 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 84921008 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 9867 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewDispSquashedInsts 341334 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 16112849 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 99067942 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21569488 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539182 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 84913582 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 10145 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 8786 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1300005 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 41358 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 16238 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1300870 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 39828 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 947297 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 703 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 947280 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 706 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 20504 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1356 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2635264 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1499501 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 20504 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 133144 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 270395 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.472085 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.472085 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 20765 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1373 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2624864 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1499472 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 20765 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 133024 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 270323 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.476021 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.476021 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47958643 56.12% 56.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 42972 0.05% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122098 0.14% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122222 0.14% 56.45% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.45% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38519 0.05% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 21787306 25.49% 81.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388360 18.01% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 48294833 56.52% 56.52% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 42901 0.05% 56.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122014 0.14% 56.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 87 0.00% 56.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122228 0.14% 56.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38521 0.05% 56.90% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 21679241 25.37% 82.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15152888 17.73% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 85460257 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 970619 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011358 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 85452764 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 905523 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.010597 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 98326 10.13% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 436344 44.96% 55.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 435949 44.91% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 99616 11.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 404792 44.70% 55.70% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 401115 44.30% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 52896239 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.615621 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720411 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 52727427 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.620651 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.723782 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 17480622 33.05% 33.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 13990970 26.45% 59.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 8059116 15.24% 74.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4840128 9.15% 83.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 4581404 8.66% 92.54% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2086569 3.94% 96.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1156021 2.19% 98.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 475188 0.90% 99.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 226221 0.43% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 17471285 33.14% 33.14% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 13743409 26.07% 59.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 8117223 15.39% 74.59% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4850961 9.20% 83.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 4579502 8.69% 92.48% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2116514 4.01% 96.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1152468 2.19% 98.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 461880 0.88% 99.56% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 234185 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 52896239 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.580625 # Inst issue rate
system.cpu.iq.iqInstsAdded 89658342 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85460257 # Number of instructions issued
system.cpu.iq.ISSUE:issued_per_cycle::total 52727427 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.584713 # Inst issue rate
system.cpu.iq.iqInstsAdded 89657627 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85452764 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9847468 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 48230 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9846565 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 47771 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 422 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6786581 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedOperandsExamined 6801202 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 13421357 # ITB accesses
system.cpu.itb.fetch_accesses 13421810 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 13394440 # ITB hits
system.cpu.itb.fetch_misses 26917 # ITB misses
system.cpu.itb.fetch_hits 13394904 # ITB hits
system.cpu.itb.fetch_misses 26906 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -343,98 +343,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143498 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34310.090850 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31208.995937 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12072 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 4509238000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915873 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131426 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4101673500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915873 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131426 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147584 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.410943 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.923979 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 103938 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1489830500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.295737 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43646 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1354463000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295737 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43646 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 161485 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 161485 # number of Writeback hits
system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.769357 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31245.328098 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12069 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 4512807000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915891 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131424 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4106386000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915891 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131424 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147532 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.347507 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.670455 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 103884 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1489896000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.295854 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43648 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1354514000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295854 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43648 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 161507 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 161507 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.759972 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.759811 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 291082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34266.293296 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 116010 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5999068500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.601453 # miss rate for demand accesses
system.cpu.l2cache.demand_accesses 291025 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34287.053327 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31192.309450 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 115953 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 6002703000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.601570 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 175072 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 5456136500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.601453 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_latency 5460900000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.601570 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 175072 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.094631 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.481096 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3100.873906 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15764.562961 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 291082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34266.293296 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.094660 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.481148 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3101.833838 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15766.259215 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 291025 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34287.053327 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31192.309450 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 116010 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5999068500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.601453 # miss rate for overall accesses
system.cpu.l2cache.overall_hits 115953 # number of overall hits
system.cpu.l2cache.overall_miss_latency 6002703000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.601570 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 175072 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 5456136500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.601453 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_latency 5460900000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.601570 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 175072 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 148714 # number of replacements
system.cpu.l2cache.replacements 148712 # number of replacements
system.cpu.l2cache.sampled_refs 174071 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18865.436867 # Cycle average of tags in use
system.cpu.l2cache.total_refs 132289 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18868.093053 # Cycle average of tags in use
system.cpu.l2cache.total_refs 132261 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120514 # number of writebacks
system.cpu.memDep0.conflictingLoads 12522416 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11202183 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 23014663 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16344120 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 54067379 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1899423 # Number of cycles rename is blocking
system.cpu.l2cache.writebacks 120513 # number of writebacks
system.cpu.memDep0.conflictingLoads 12487229 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11176863 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 22901502 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16112849 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 53923173 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1782763 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 50756 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 28921656 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1270692 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 121761220 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 101056260 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 60792051 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 19304913 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1300005 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1392613 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8245170 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 77629 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5282 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2690297 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5280 # count of temporary serializing insts renamed
system.cpu.timesIdled 40629 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 52474 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 28901078 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1299024 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 36 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 121755454 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 101053942 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 60784194 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 19225803 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1300870 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1439133 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8237313 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 77780 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5276 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 3015491 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5274 # count of temporary serializing insts renamed
system.cpu.timesIdled 39379 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

3
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

11
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 02:20:31
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:44:15
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 44221003000 because target called exit()

10
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3163275 # Simulator instruction rate (inst/s)
host_mem_usage 192676 # Number of bytes of host memory used
host_seconds 27.93 # Real time elapsed on the host
host_tick_rate 1583437342 # Simulator tick rate (ticks/s)
host_inst_rate 5477905 # Simulator instruction rate (inst/s)
host_mem_usage 240580 # Number of bytes of host memory used
host_seconds 16.13 # Real time elapsed on the host
host_tick_rate 2742055845 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated
@ -44,7 +44,7 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.num_refs 34987415 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

12
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:47:45
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:40:34
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1350777 # Simulator instruction rate (inst/s)
host_mem_usage 201544 # Number of bytes of host memory used
host_seconds 65.40 # Real time elapsed on the host
host_tick_rate 2053162286 # Simulator tick rate (ticks/s)
host_inst_rate 2249900 # Simulator instruction rate (inst/s)
host_mem_usage 248308 # Number of bytes of host memory used
host_seconds 39.26 # Real time elapsed on the host
host_tick_rate 3419804648 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.134277 # Number of seconds simulated
@ -233,7 +233,7 @@ system.cpu.l2cache.writebacks 120506 # nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 268553976 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.num_refs 34987415 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

14
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:52
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:41:19
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -28,4 +30,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 725600064000 because target called exit()
Exiting @ tick 723991197000 because target called exit()

648
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 201279 # Simulator instruction rate (inst/s)
host_mem_usage 193732 # Number of bytes of host memory used
host_seconds 8625.07 # Real time elapsed on the host
host_tick_rate 84126874 # Simulator tick rate (ticks/s)
host_inst_rate 217413 # Simulator instruction rate (inst/s)
host_mem_usage 240500 # Number of bytes of host memory used
host_seconds 7985.01 # Real time elapsed on the host
host_tick_rate 90668752 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.725600 # Number of seconds simulated
sim_ticks 725600064000 # Number of ticks simulated
sim_seconds 0.723991 # Number of seconds simulated
sim_ticks 723991197000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 297121632 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 303782824 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 142 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 19928405 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 265297852 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 344822488 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 23968882 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 297134991 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 303959521 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 19913428 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 265314839 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 344584799 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 23886075 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 61479856 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 63016645 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1350419468 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.347567 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.103580 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1347786892 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.350199 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.111631 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 709166800 52.51% 52.51% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 257980850 19.10% 71.62% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 128756395 9.53% 81.15% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 75319653 5.58% 86.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 50577217 3.75% 90.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 29303662 2.17% 92.65% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 27183744 2.01% 94.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10651291 0.79% 95.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 61479856 4.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 706265401 52.40% 52.40% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 261524956 19.40% 71.81% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 126857294 9.41% 81.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 73810788 5.48% 86.69% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 49267201 3.66% 90.35% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 31663388 2.35% 92.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 24079219 1.79% 94.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 11302000 0.84% 95.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 63016645 4.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1350419468 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1347786892 # Number of insts commited each cycle
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
system.cpu.commit.COM:loads 445666361 # Number of loads committed
system.cpu.commit.COM:loads 444595663 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:refs 605324165 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19927893 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 19912897 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 598409142 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 594069052 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.835924 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.835924 # CPI: Total CPI of All Threads
system.cpu.cpi 0.834070 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.834070 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
@ -59,289 +59,289 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 522152433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16274.867726 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10956.764593 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 512203202 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 161922418500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019054 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 9949231 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 2672880 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 79725265000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013935 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7276351 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_accesses 521802290 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16279.064598 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10961.675998 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 511855593 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 161922923000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019062 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 9946697 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 2670317 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 79761320000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013945 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7276380 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26917.452067 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20483.226007 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155989745 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 127555264405 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.029483 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4738757 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2853938 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 38607173559 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 27145.945678 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20467.767187 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155989397 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 128647486892 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.029485 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4739105 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2854288 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 38577995547 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011727 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1884819 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.492044 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_misses 1884817 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3153.493916 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 30417.808324 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 72.937504 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 37706 # number of cycles access was blocked
system.cpu.dcache.avg_refs 72.899308 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 37723 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65110 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 118943277 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 118959251 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1980503500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 682880935 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19708.464012 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12916.738644 # average overall mshr miss latency
system.cpu.dcache.demand_hits 668192947 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 289477682905 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.021509 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14687988 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5526818 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 118332438559 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013415 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9161170 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 682530792 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19785.804677 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12917.451240 # average overall mshr miss latency
system.cpu.dcache.demand_hits 667844990 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 290570409892 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.021517 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14685802 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5524605 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 118339315547 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013422 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9161197 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997445 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4085.532750 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 682880935 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19708.464012 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12916.738644 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.997439 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4085.509480 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 682530792 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19785.804677 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12917.451240 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 668192947 # number of overall hits
system.cpu.dcache.overall_miss_latency 289477682905 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.021509 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14687988 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5526818 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 118332438559 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013415 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9161170 # number of overall MSHR misses
system.cpu.dcache.overall_hits 667844990 # number of overall hits
system.cpu.dcache.overall_miss_latency 290570409892 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.021517 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14685802 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5524605 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 118339315547 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013422 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9161197 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9157075 # number of replacements
system.cpu.dcache.sampled_refs 9161171 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 9157102 # number of replacements
system.cpu.dcache.sampled_refs 9161198 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4085.532750 # Cycle average of tags in use
system.cpu.dcache.total_refs 668192949 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7084076000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3077872 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 79445863 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 739 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 54863160 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2804005174 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 723465377 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 543368654 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 89450574 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1719 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 4139574 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 765936230 # DTB accesses
system.cpu.dcache.tagsinuse 4085.509480 # Cycle average of tags in use
system.cpu.dcache.total_refs 667844992 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7084078000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3077854 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 78806586 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 620 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 54720823 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2797425384 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 722637583 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 541899569 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 88987438 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1777 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 4443154 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 767802302 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 750636298 # DTB hits
system.cpu.dtb.data_misses 15299932 # DTB misses
system.cpu.dtb.data_hits 752449535 # DTB hits
system.cpu.dtb.data_misses 15352767 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 565223455 # DTB read accesses
system.cpu.dtb.read_accesses 566812903 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 556102001 # DTB read hits
system.cpu.dtb.read_misses 9121454 # DTB read misses
system.cpu.dtb.write_accesses 200712775 # DTB write accesses
system.cpu.dtb.read_hits 557652499 # DTB read hits
system.cpu.dtb.read_misses 9160404 # DTB read misses
system.cpu.dtb.write_accesses 200989399 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 194534297 # DTB write hits
system.cpu.dtb.write_misses 6178478 # DTB write misses
system.cpu.fetch.Branches 344822488 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355034186 # Number of cache lines fetched
system.cpu.fetch.Cycles 913253672 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8462729 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2857790040 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28218175 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.237612 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355034186 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 321090514 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.969260 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1439870042 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.984756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.874458 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 194797036 # DTB write hits
system.cpu.dtb.write_misses 6192363 # DTB write misses
system.cpu.fetch.Branches 344584799 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 354412327 # Number of cache lines fetched
system.cpu.fetch.Cycles 911372250 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8690810 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2851036906 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28190849 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.237976 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 354412327 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 321021066 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.968972 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1436774330 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.984332 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.873889 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 881650589 61.23% 61.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48391639 3.36% 64.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30824264 2.14% 66.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 51186075 3.55% 70.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 123166257 8.55% 78.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 68161636 4.73% 83.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 47264733 3.28% 86.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36668750 2.55% 89.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 152556099 10.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 879814440 61.24% 61.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48078779 3.35% 64.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 31070380 2.16% 66.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 51055446 3.55% 70.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 122790894 8.55% 78.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 67990825 4.73% 83.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 47151543 3.28% 86.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36952114 2.57% 89.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 151869909 10.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1439870042 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 355034186 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35334.265176 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35459.890110 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355032934 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44238500 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 1436774330 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 354412327 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35305.051302 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 354411060 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44731500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1252 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 342 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32268500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 1267 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 346 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32661000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 921 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 390146.081319 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 384811.140065 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 355034186 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35334.265176 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35459.890110 # average overall mshr miss latency
system.cpu.icache.demand_hits 355032934 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44238500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 354412327 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35305.051302 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35462.540717 # average overall mshr miss latency
system.cpu.icache.demand_hits 354411060 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44731500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1252 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 342 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32268500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 1267 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32661000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 921 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.349698 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 716.180731 # Average occupied blocks per context
system.cpu.icache.overall_accesses 355034186 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35334.265176 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35459.890110 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.352268 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 721.445735 # Average occupied blocks per context
system.cpu.icache.overall_accesses 354412327 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35305.051302 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35462.540717 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 355032934 # number of overall hits
system.cpu.icache.overall_miss_latency 44238500 # number of overall miss cycles
system.cpu.icache.overall_hits 354411060 # number of overall hits
system.cpu.icache.overall_miss_latency 44731500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1252 # number of overall misses
system.cpu.icache.overall_mshr_hits 342 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32268500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 1267 # number of overall misses
system.cpu.icache.overall_mshr_hits 346 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32661000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 921 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
system.cpu.icache.sampled_refs 921 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 716.180731 # Cycle average of tags in use
system.cpu.icache.total_refs 355032934 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 721.445735 # Cycle average of tags in use
system.cpu.icache.total_refs 354411060 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 11330087 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 280332781 # Number of branches executed
system.cpu.iew.EXEC:nop 129121920 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.560467 # Inst execution rate
system.cpu.iew.EXEC:refs 767231280 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 200922716 # Number of stores executed
system.cpu.idleCycles 11208065 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 280169878 # Number of branches executed
system.cpu.iew.EXEC:nop 129057525 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.565430 # Inst execution rate
system.cpu.iew.EXEC:refs 767802324 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 200989407 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1522686548 # num instructions consuming a value
system.cpu.iew.WB:count 2225893734 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811633 # average fanout of values written-back
system.cpu.iew.WB:consumers 1523016532 # num instructions consuming a value
system.cpu.iew.WB:count 2228484684 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811571 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1235862105 # num instructions producing a value
system.cpu.iew.WB:rate 1.533830 # insts written-back per cycle
system.cpu.iew.WB:sent 2246790117 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21706516 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 15735224 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 619699188 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 21567119 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 233370796 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2608680423 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 566308564 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 37529963 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2264549792 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 297607 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1236036667 # num instructions producing a value
system.cpu.iew.WB:rate 1.539027 # insts written-back per cycle
system.cpu.iew.WB:sent 2249496581 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21722236 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 15314374 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 617102957 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 21692258 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 232568585 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2603343055 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 566812917 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 38578662 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2266715425 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 389623 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 27486 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 89450574 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 675659 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 88987438 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 694096 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 161623 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 33872925 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 214320 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 161793 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 35773426 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 210663 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 2995791 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.memOrderViolation 2851639 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 17 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 174032827 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 72465814 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2995791 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3378494 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18328022 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.196281 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.196281 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.squashedLoads 172507294 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 71840083 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2851639 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3390000 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18332236 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.198940 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.198940 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1521321100 66.08% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 97 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 232 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 138 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 576616052 25.05% 91.13% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 204142076 8.87% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1523557218 66.09% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 93 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 225 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 139 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 15 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 577672336 25.06% 91.15% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 204064018 8.85% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2302079755 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12945104 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005623 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 2305294087 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 13339064 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005786 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 2890284 22.33% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 8361572 64.59% 86.92% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1693248 13.08% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 3077619 23.07% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 8405753 63.02% 86.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1855692 13.91% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1439870042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.598811 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.750982 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1436774330 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.604493 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.761639 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 553825571 38.46% 38.46% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 266666629 18.52% 56.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 241255351 16.76% 73.74% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 143700504 9.98% 83.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 114580764 7.96% 91.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 70398755 4.89% 96.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 36702113 2.55% 99.12% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10651437 0.74% 99.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 2088918 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 552319838 38.44% 38.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 267044119 18.59% 57.03% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 243823244 16.97% 74.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 135766343 9.45% 83.45% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 111649965 7.77% 91.22% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 72620793 5.05% 96.27% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 43154972 3.00% 99.28% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 8489654 0.59% 99.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 1905402 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1439870042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.586328 # Inst issue rate
system.cpu.iq.iqInstsAdded 2479558460 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2302079755 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 726499267 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 996261 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 330157127 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 1436774330 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.592073 # Inst issue rate
system.cpu.iq.iqInstsAdded 2474285485 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2305294087 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 718781925 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1290278 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 318719479 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 355034219 # ITB accesses
system.cpu.itb.fetch_accesses 354412360 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 355034186 # ITB hits
system.cpu.itb.fetch_hits 354412327 # ITB hits
system.cpu.itb.fetch_misses 33 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -351,98 +351,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1884821 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34451.716970 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31263.065922 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 1001550 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 30430202500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.468623 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27613759500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468623 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7277260 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34300.261562 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.501409 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5456659 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 62447090500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.250177 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1820601 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685325000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250177 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1820601 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3077872 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3077872 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10336.866902 # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_accesses 1884819 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34457.281872 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31270.548143 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 1001564 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 30434566500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.468615 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 883255 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27619868000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468615 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 883255 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7277300 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34308.231469 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.566655 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5456738 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 62460262500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.250170 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1820562 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56684229500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250170 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1820562 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3077854 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3077854 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10339.327830 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.807813 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 1698 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 2.807892 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 1696 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 17552000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 17535500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9162081 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34349.737340 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.172773 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6458209 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 92877293000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.295115 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2703872 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 9162119 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34356.921715 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31179.661013 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6458302 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 92894829000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2703817 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 84299084500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.295115 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2703872 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 84304097500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2703817 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.484528 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.327269 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15877.018497 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10723.955560 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9162081 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34349.737340 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.172773 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.484040 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.327555 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15861.025964 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10733.328518 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9162119 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34356.921715 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31179.661013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 6458209 # number of overall hits
system.cpu.l2cache.overall_miss_latency 92877293000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.295115 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2703872 # number of overall misses
system.cpu.l2cache.overall_hits 6458302 # number of overall hits
system.cpu.l2cache.overall_miss_latency 92894829000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2703817 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 84299084500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.295115 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2703872 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 84304097500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2703817 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2693288 # number of replacements
system.cpu.l2cache.sampled_refs 2717930 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 2693237 # number of replacements
system.cpu.l2cache.sampled_refs 2717881 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 26600.974057 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7631439 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 148178401500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1171803 # number of writebacks
system.cpu.memDep0.conflictingLoads 134698193 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 69978801 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 619699188 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 233370796 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1451200129 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 52056982 # Number of cycles rename is blocking
system.cpu.l2cache.tagsinuse 26594.354482 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7631516 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 148066834500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1171784 # number of writebacks
system.cpu.memDep0.conflictingLoads 123159990 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 64312407 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 617102957 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 232568585 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1447982395 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 51393371 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 6212885 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 741942603 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 18353930 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 492222 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3542299573 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2739870490 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2052189295 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 529159748 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 89450574 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 27259412 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 675986332 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 723 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 54988572 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
system.cpu.timesIdled 434261 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 5887635 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 740841122 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 18541128 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 493389 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3535273918 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2734162916 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2047681663 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 528076479 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 88987438 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 27475071 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 671478700 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 54007891 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
system.cpu.timesIdled 425188 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

3
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

11
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,10 +7,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:01:37
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:35:16
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -28,3 +30,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 913189263000 because target called exit()

10
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1736234 # Simulator instruction rate (inst/s)
host_mem_usage 184024 # Number of bytes of host memory used
host_seconds 1048.12 # Real time elapsed on the host
host_tick_rate 871264314 # Simulator tick rate (ticks/s)
host_inst_rate 5747960 # Simulator instruction rate (inst/s)
host_mem_usage 231948 # Number of bytes of host memory used
host_seconds 316.60 # Real time elapsed on the host
host_tick_rate 2884399053 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 0.913189 # Number of seconds simulated
@ -44,7 +44,7 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 613169725 # Number of memory references
system.cpu.num_refs 611922547 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

12
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:33:53
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:53:28
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1370976 # Simulator instruction rate (inst/s)
host_mem_usage 192892 # Number of bytes of host memory used
host_seconds 1327.36 # Real time elapsed on the host
host_tick_rate 2006569980 # Simulator tick rate (ticks/s)
host_inst_rate 2423488 # Simulator instruction rate (inst/s)
host_mem_usage 239668 # Number of bytes of host memory used
host_seconds 750.89 # Real time elapsed on the host
host_tick_rate 3547033530 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.663444 # Number of seconds simulated
@ -233,7 +233,7 @@ system.cpu.l2cache.writebacks 1170923 # nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 613169725 # Number of memory references
system.cpu.num_refs 611922547 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -186,12 +186,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

4
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr
View file

@ -1,9 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetching currently unimplemented
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

13
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,12 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:52:34
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:31:02
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

30
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 54763 # Simulator instruction rate (inst/s)
host_mem_usage 197304 # Number of bytes of host memory used
host_seconds 1678.20 # Real time elapsed on the host
host_tick_rate 58595727 # Simulator tick rate (ticks/s)
host_inst_rate 68324 # Simulator instruction rate (inst/s)
host_mem_usage 244132 # Number of bytes of host memory used
host_seconds 1345.11 # Real time elapsed on the host
host_tick_rate 73105878 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.098335 # Number of seconds simulated
sim_ticks 98335161000 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations
system.cpu.AGEN-Unit.agens 26497301 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups 8584401 # Number of BTB lookups
@ -19,7 +19,7 @@ system.cpu.Branch-Predictor.lookups 10240685 # Nu
system.cpu.Branch-Predictor.predictedNotTaken 2702033 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 7538652 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target.
system.cpu.Execution-Unit.executions 64907696 # Number of Instructions Executed.
system.cpu.Execution-Unit.executions 64947503 # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct 22.664900 # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted 2321041 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 7919644 # Number of Branches Incorrectly Predicted
@ -31,14 +31,14 @@ system.cpu.RegFile-Manager.regFileAccesses 185972268 #
system.cpu.RegFile-Manager.regFileReads 117544907 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards 2843090 # Number of Registers Read Through Forwarding Logic
system.cpu.activity 95.462227 # Percentage of cycles cpu is active
system.cpu.activity 95.462226 # Percentage of cycles cpu is active
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.comInts 43625545 # Number of Integer instructions committed
system.cpu.comLoads 20034413 # Number of Load instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comStores 6502695 # Number of Store instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
@ -181,7 +181,7 @@ system.cpu.icache.tagsinuse 1428.759296 # Cy
system.cpu.icache.total_refs 101754083 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 8924453 # Number of cycles cpu's stages were not processed
system.cpu.idleCycles 8924455 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.467295 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.467295 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
@ -270,7 +270,7 @@ system.cpu.l2cache.total_refs 5998 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 196670323 # number of cpu cycles simulated
system.cpu.runCycles 187745870 # Number of cycles cpu stages are processed.
system.cpu.runCycles 187745868 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
@ -284,9 +284,9 @@ system.cpu.stage-1.utilization 46.860407 # Pe
system.cpu.stage-2.idleCycles 103177839 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 47.537667 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 170133192 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 13.493206 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 170172999 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 26497324 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 13.472965 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 104767267 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization 46.729499 # Percentage of cycles stage was utilized (processing insts).

4
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

15
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,12 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:34:48
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:27:52
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -27,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 40701237000 because target called exit()
122 123 124 Exiting @ tick 40631511500 because target called exit()

624
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,340 +1,340 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 172806 # Simulator instruction rate (inst/s)
host_mem_usage 197872 # Number of bytes of host memory used
host_seconds 487.13 # Real time elapsed on the host
host_tick_rate 83552440 # Simulator tick rate (ticks/s)
host_inst_rate 191238 # Simulator instruction rate (inst/s)
host_mem_usage 244496 # Number of bytes of host memory used
host_seconds 440.18 # Real time elapsed on the host
host_tick_rate 92306061 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.040701 # Number of seconds simulated
sim_ticks 40701237000 # Number of ticks simulated
sim_seconds 0.040632 # Number of seconds simulated
sim_ticks 40631511500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 11915545 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 15874334 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1218 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1889899 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 14602096 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 19578655 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1736849 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 11932962 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 15864027 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1214 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1885603 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 14586720 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 19564106 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1732867 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 10240685 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 2864912 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 2884434 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 73200571 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.255496 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.951465 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 73022923 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.258551 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.953672 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 35883667 49.02% 49.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 18420857 25.16% 74.19% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 7399798 10.11% 84.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3793136 5.18% 89.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2033346 2.78% 92.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1324316 1.81% 94.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 734839 1.00% 95.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 745700 1.02% 96.09% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 2864912 3.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 35697739 48.89% 48.89% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 18400471 25.20% 74.08% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 7461073 10.22% 84.30% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3811930 5.22% 89.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 1995705 2.73% 92.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1288642 1.76% 94.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 737357 1.01% 95.03% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 745572 1.02% 96.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 2884434 3.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 73200571 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 73022923 # Number of insts commited each cycle
system.cpu.commit.COM:count 91903055 # Number of instructions committed
system.cpu.commit.COM:loads 20034413 # Number of loads committed
system.cpu.commit.COM:loads 19996198 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:refs 26497301 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1876760 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 1872416 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 56257975 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 56371965 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.967008 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.967008 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 23361980 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30151.634724 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32163.725490 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23361093 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 26744500 # number of ReadReq miss cycles
system.cpu.cpi 0.965352 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.965352 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 23336477 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30318.337130 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32167.647059 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23335599 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 26619500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 887 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 377 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 16403500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 878 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 368 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 16405500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 35569.269207 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35483.256351 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493098 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 284732000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001231 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 8005 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6273 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 61457000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 35388.341031 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35272.360069 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493092 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 283496000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001232 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 8011 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6278 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 61127000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 13315.879572 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 13298.573785 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 29863083 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35028.846154 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29854191 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 311476500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_accesses 29837580 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 34887.557656 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29828691 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 310115500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
system.cpu.dcache.demand_misses 8892 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6650 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 77860500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_misses 8889 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6646 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 77532500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.356508 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1460.254824 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 29863083 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35028.846154 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.356524 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1460.322095 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 29837580 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34887.557656 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 29854191 # number of overall hits
system.cpu.dcache.overall_miss_latency 311476500 # number of overall miss cycles
system.cpu.dcache.overall_hits 29828691 # number of overall hits
system.cpu.dcache.overall_miss_latency 310115500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
system.cpu.dcache.overall_misses 8892 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6650 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 77860500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_misses 8889 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6646 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 77532500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 160 # number of replacements
system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1460.254824 # Cycle average of tags in use
system.cpu.dcache.total_refs 29854202 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1460.322095 # Cycle average of tags in use
system.cpu.dcache.total_refs 29828701 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 109 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 4195761 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 13279 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3138343 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162326891 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 39347906 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29437041 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8093015 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 48049 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 219863 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 31798533 # DTB accesses
system.cpu.decode.DECODE:BlockedCycles 3982765 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3143444 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162519421 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 39357415 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29479520 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8131535 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 48925 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 203223 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 31749224 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 31420024 # DTB hits
system.cpu.dtb.data_misses 378509 # DTB misses
system.cpu.dtb.data_hits 31371389 # DTB hits
system.cpu.dtb.data_misses 377835 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 24587243 # DTB read accesses
system.cpu.dtb.read_accesses 24565202 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 24209793 # DTB read hits
system.cpu.dtb.read_misses 377450 # DTB read misses
system.cpu.dtb.write_accesses 7211290 # DTB write accesses
system.cpu.dtb.read_hits 24188408 # DTB read hits
system.cpu.dtb.read_misses 376794 # DTB read misses
system.cpu.dtb.write_accesses 7184022 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 7210231 # DTB write hits
system.cpu.dtb.write_misses 1059 # DTB write misses
system.cpu.fetch.Branches 19578655 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19042384 # Number of cache lines fetched
system.cpu.fetch.Cycles 49581925 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 482421 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167418269 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2029286 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.240517 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19042384 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 13652394 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.056673 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 81293586 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.059428 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.087450 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 7182981 # DTB write hits
system.cpu.dtb.write_misses 1041 # DTB write misses
system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched
system.cpu.fetch.Cycles 49623738 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 13665829 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.062844 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 81154458 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.065603 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.090223 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 50754116 62.43% 62.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3139628 3.86% 66.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1895979 2.33% 68.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3231029 3.97% 72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4381369 5.39% 77.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1498108 1.84% 79.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1855702 2.28% 82.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1657872 2.04% 84.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 12879783 15.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 50590239 62.34% 62.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3137902 3.87% 66.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1890959 2.33% 68.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3231189 3.98% 72.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4367674 5.38% 77.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1502603 1.85% 79.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1888200 2.33% 82.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1658917 2.04% 84.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 12886775 15.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 81293586 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 19042384 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15742.896836 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11872.070120 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 19031227 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 175643500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000586 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 11157 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120549000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000533 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10154 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 81154458 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 19059447 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15766.588953 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 19048295 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 175829000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 11152 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1015 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120621000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1874.259110 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1879.086022 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 19042384 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15742.896836 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency
system.cpu.icache.demand_hits 19031227 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 175643500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000586 # miss rate for demand accesses
system.cpu.icache.demand_misses 11157 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120549000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000533 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10154 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 19059447 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15766.588953 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency
system.cpu.icache.demand_hits 19048295 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 175829000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses
system.cpu.icache.demand_misses 11152 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1015 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120621000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.756089 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1548.470149 # Average occupied blocks per context
system.cpu.icache.overall_accesses 19042384 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15742.896836 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.756347 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1548.997868 # Average occupied blocks per context
system.cpu.icache.overall_accesses 19059447 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15766.588953 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 19031227 # number of overall hits
system.cpu.icache.overall_miss_latency 175643500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000586 # miss rate for overall accesses
system.cpu.icache.overall_misses 11157 # number of overall misses
system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120549000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000533 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10154 # number of overall MSHR misses
system.cpu.icache.overall_hits 19048295 # number of overall hits
system.cpu.icache.overall_miss_latency 175829000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses
system.cpu.icache.overall_misses 11152 # number of overall misses
system.cpu.icache.overall_mshr_hits 1015 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120621000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 8238 # number of replacements
system.cpu.icache.sampled_refs 10154 # Sample count of references to valid blocks.
system.cpu.icache.replacements 8219 # number of replacements
system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1548.470149 # Cycle average of tags in use
system.cpu.icache.total_refs 19031227 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1548.997868 # Cycle average of tags in use
system.cpu.icache.total_refs 19048295 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 108889 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12932789 # Number of branches executed
system.cpu.iew.EXEC:nop 12752151 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.252018 # Inst execution rate
system.cpu.iew.EXEC:refs 31851951 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7212939 # Number of stores executed
system.cpu.idleCycles 108566 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12934750 # Number of branches executed
system.cpu.iew.EXEC:nop 12801851 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.253335 # Inst execution rate
system.cpu.iew.EXEC:refs 31749416 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7184063 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 91351431 # num instructions consuming a value
system.cpu.iew.WB:count 100121785 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.722504 # average fanout of values written-back
system.cpu.iew.WB:consumers 91396336 # num instructions consuming a value
system.cpu.iew.WB:count 100051870 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.721943 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 66001783 # num instructions producing a value
system.cpu.iew.WB:rate 1.229960 # insts written-back per cycle
system.cpu.iew.WB:sent 100960101 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2058583 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 308073 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 33906754 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1495766 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10659940 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 148159865 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24639012 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2167407 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 101917357 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 147057 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 65982976 # num instructions producing a value
system.cpu.iew.WB:rate 1.231210 # insts written-back per cycle
system.cpu.iew.WB:sent 100889956 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2057434 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 253528 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 33850050 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1485832 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10655807 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 148273965 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24565353 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2165750 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 101849758 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 124164 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 229 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8093015 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 184742 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 47 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8131535 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 157443 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 837974 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2531 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 842082 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2486 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 262379 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9827 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13872341 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4157245 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 262379 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 456408 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1602175 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.034117 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.034117 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 268955 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9838 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13853852 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4154704 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 268955 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 456787 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1600647 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.035892 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.035892 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580956 62.05% 62.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 474234 0.46% 62.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786797 2.68% 65.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114549 0.11% 65.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387018 2.29% 67.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305140 0.29% 67.88% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 754986 0.73% 68.60% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.60% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 25334340 24.34% 92.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346414 7.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 64603279 62.11% 62.11% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 474408 0.46% 62.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2788350 2.68% 65.25% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114559 0.11% 65.36% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2389553 2.30% 67.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305056 0.29% 67.95% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755116 0.73% 68.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 25265594 24.29% 92.96% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7319262 7.04% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 104084764 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 1605421 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.015424 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 104015508 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 1951419 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.018761 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 233590 14.55% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 339 0.02% 14.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.57% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 3702 0.23% 14.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 2371 0.15% 14.95% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 538253 33.53% 48.48% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 48.48% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 750644 46.76% 95.23% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 76522 4.77% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 264504 13.55% 13.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 67 0.00% 13.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 1979 0.10% 13.66% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 2355 0.12% 13.78% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 826053 42.33% 56.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 56.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 733480 37.59% 93.70% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 122981 6.30% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 81293586 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280356 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539590 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 81154458 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.281698 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540203 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 34992440 43.04% 43.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 18916491 23.27% 66.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 11753286 14.46% 80.77% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 6613191 8.13% 88.91% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 5113111 6.29% 95.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2406044 2.96% 98.16% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1201508 1.48% 99.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 249704 0.31% 99.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 47811 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 34964609 43.08% 43.08% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 18826048 23.20% 66.28% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 11595868 14.29% 80.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 6807186 8.39% 88.96% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 5054639 6.23% 95.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2409288 2.97% 98.16% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1203500 1.48% 99.64% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 256390 0.32% 99.95% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 36930 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 81293586 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.278644 # Inst issue rate
system.cpu.iq.iqInstsAdded 135407278 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 104084764 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 50574577 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 302079 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47259225 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 81154458 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.279986 # Inst issue rate
system.cpu.iq.iqInstsAdded 135471680 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 104015508 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 50629869 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 304728 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47460542 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 19042455 # ITB accesses
system.cpu.itb.fetch_accesses 19059519 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 19042384 # ITB hits
system.cpu.itb.fetch_misses 71 # ITB misses
system.cpu.itb.fetch_hits 19059447 # ITB hits
system.cpu.itb.fetch_misses 72 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -343,97 +343,97 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34699.413490 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31528.152493 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34492.672919 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31439.624853 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 27 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 59162500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.984411 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1705 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53755500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1705 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10664 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34281.213192 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.566549 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7268 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 116419000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.318455 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3396 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105553000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318455 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3396 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_miss_latency 58844500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.984420 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53636000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984420 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10647 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34284.558824 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.500000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7247 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 116567500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.319339 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3400 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105680500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319339 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3400 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.100462 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.091984 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12396 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34420.995883 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7295 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 175581500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.411504 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5101 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 12380 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34354.093224 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7274 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 175412000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.412439 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5106 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 159308500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.411504 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5101 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 159316500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.412439 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5106 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.070268 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000537 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2302.534301 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.609654 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 12396 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34420.995883 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.070256 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000538 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2302.164021 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.613547 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 12380 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34354.093224 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7295 # number of overall hits
system.cpu.l2cache.overall_miss_latency 175581500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.411504 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5101 # number of overall misses
system.cpu.l2cache.overall_hits 7274 # number of overall hits
system.cpu.l2cache.overall_miss_latency 175412000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.412439 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5106 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 159308500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.411504 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 159316500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.412439 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5106 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3464 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 3468 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2320.143954 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7276 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2319.777568 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7255 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 17616969 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5053323 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 33906754 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10659940 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 81402475 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1958550 # Number of cycles rename is blocking
system.cpu.memDep0.conflictingLoads 17824866 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5359806 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 33850050 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10655807 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 81263024 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1835260 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1204707 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 40603552 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 943829 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202471233 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157096154 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 115391431 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28385991 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8093015 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 2247276 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 46964070 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 5202 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 471 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4950569 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 460 # count of temporary serializing insts renamed
system.cpu.timesIdled 2416 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 1124456 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 40588679 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 939622 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202646679 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157276395 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 115514667 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28432140 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8131535 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 2161646 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 47087306 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 5198 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4785663 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed
system.cpu.timesIdled 2403 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

3
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

12
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,10 +7,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:01:12
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:32:41
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -26,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124
122 123 124 Exiting @ tick 45951567500 because target called exit()

10
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1794306 # Simulator instruction rate (inst/s)
host_mem_usage 187928 # Number of bytes of host memory used
host_seconds 51.22 # Real time elapsed on the host
host_tick_rate 897149357 # Simulator tick rate (ticks/s)
host_inst_rate 4196549 # Simulator instruction rate (inst/s)
host_mem_usage 235848 # Number of bytes of host memory used
host_seconds 21.90 # Real time elapsed on the host
host_tick_rate 2098254960 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated
@ -44,7 +44,7 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 91903136 # number of cpu cycles simulated
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537141 # Number of memory references
system.cpu.num_refs 26497334 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
View file

@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

12
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:52
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:35:14
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1097596 # Simulator instruction rate (inst/s)
host_mem_usage 196804 # Number of bytes of host memory used
host_seconds 83.73 # Real time elapsed on the host
host_tick_rate 1418103765 # Simulator tick rate (ticks/s)
host_inst_rate 2386222 # Simulator instruction rate (inst/s)
host_mem_usage 243572 # Number of bytes of host memory used
host_seconds 38.51 # Real time elapsed on the host
host_tick_rate 3083013039 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118740 # Number of seconds simulated
@ -233,7 +233,7 @@ system.cpu.l2cache.writebacks 0 # nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 237480098 # number of cpu cycles simulated
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537141 # Number of memory references
system.cpu.num_refs 26497334 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

14
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -1,5 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simerr
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:04
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 22:53:27
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

38
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 34398 # Simulator instruction rate (inst/s)
host_mem_usage 203876 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 104794717 # Simulator tick rate (ticks/s)
host_inst_rate 101462 # Simulator instruction rate (inst/s)
host_mem_usage 236800 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 307213198 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000007 # Number of seconds simulated
@ -228,7 +228,7 @@ system.cpu.idleCycles 7900 # To
system.cpu.iew.EXEC:branches 601 # Number of branches executed
system.cpu.iew.EXEC:nop 306 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate
system.cpu.iew.EXEC:refs 1019 # number of memory reference insts executed
system.cpu.iew.EXEC:refs 1017 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 368 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1981 # num instructions consuming a value
@ -241,12 +241,12 @@ system.cpu.iew.WB:rate 0.232998 # in
system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 793 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 651 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts 649 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
@ -262,7 +262,7 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 380 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedLoads 378 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly
@ -270,16 +270,16 @@ system.cpu.iew.predictedTakenIncorrect 55 # Nu
system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 2582 71.11% 71.11% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 675 18.59% 89.73% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 2584 71.16% 71.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 673 18.53% 89.73% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
@ -406,7 +406,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 14601 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking

2
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864

10
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,10 +7,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 02:37:14
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:32:40
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

6
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 794145 # Simulator instruction rate (inst/s)
host_mem_usage 181656 # Number of bytes of host memory used
host_inst_rate 759729 # Simulator instruction rate (inst/s)
host_mem_usage 228516 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 371138444 # Simulator tick rate (ticks/s)
host_tick_rate 362937063 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/home/stever/m5/m5_system_2.0b3/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -265,7 +265,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -285,7 +285,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -411,7 +411,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

15
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,14 +7,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:53
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
M5 compiled Nov 2 2010 23:00:12
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 23:09:56
M5 executing on aus-bc2-b15
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
Exiting @ tick 1870335522500 because m5_exit instruction encountered

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2584495 # Simulator instruction rate (inst/s)
host_mem_usage 281712 # Number of bytes of host memory used
host_seconds 24.44 # Real time elapsed on the host
host_tick_rate 76540345609 # Simulator tick rate (ticks/s)
host_inst_rate 4418519 # Simulator instruction rate (inst/s)
host_mem_usage 326752 # Number of bytes of host memory used
host_seconds 14.29 # Real time elapsed on the host
host_tick_rate 130854140423 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63154034 # Number of instructions simulated
sim_seconds 1.870336 # Number of seconds simulated
@ -306,7 +306,7 @@ system.cpu0.kern.syscall::total 226 # nu
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
system.cpu0.num_insts 57222076 # Number of instructions executed
system.cpu0.num_refs 15330887 # Number of memory references
system.cpu0.num_refs 15135515 # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits
@ -588,7 +588,7 @@ system.cpu1.kern.syscall::total 100 # nu
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
system.cpu1.num_insts 5931958 # Number of instructions executed
system.cpu1.num_refs 1926645 # Number of memory references
system.cpu1.num_refs 1926244 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/home/stever/m5/m5_system_2.0b3/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -158,7 +158,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -178,7 +178,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -304,7 +304,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

15
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,13 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:53
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
M5 compiled Nov 2 2010 23:00:12
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 23:09:41
M5 executing on aus-bc2-b15
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332258000 because m5_exit instruction encountered

10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2709831 # Simulator instruction rate (inst/s)
host_mem_usage 280300 # Number of bytes of host memory used
host_seconds 22.16 # Real time elapsed on the host
host_tick_rate 82566195794 # Simulator tick rate (ticks/s)
host_inst_rate 4413707 # Simulator instruction rate (inst/s)
host_mem_usage 325356 # Number of bytes of host memory used
host_seconds 13.60 # Real time elapsed on the host
host_tick_rate 134480396261 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60038305 # Number of instructions simulated
sim_seconds 1.829332 # Number of seconds simulated
@ -298,7 +298,7 @@ system.cpu.kern.syscall::total 326 # nu
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
system.cpu.num_insts 60038305 # Number of instructions executed
system.cpu.num_refs 16311238 # Number of memory references
system.cpu.num_refs 16115709 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/home/stever/m5/m5_system_2.0b3/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -259,7 +259,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -279,7 +279,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -405,7 +405,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

15
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,14 +7,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:16:21
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
M5 compiled Nov 2 2010 23:00:12
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 23:10:42
M5 executing on aus-bc2-b15
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 562628000
Exiting @ tick 1958647095000 because m5_exit instruction encountered

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1372828 # Simulator instruction rate (inst/s)
host_mem_usage 278528 # Number of bytes of host memory used
host_seconds 43.24 # Real time elapsed on the host
host_tick_rate 45301058959 # Simulator tick rate (ticks/s)
host_inst_rate 1781653 # Simulator instruction rate (inst/s)
host_mem_usage 323564 # Number of bytes of host memory used
host_seconds 33.32 # Real time elapsed on the host
host_tick_rate 58791386546 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 59355643 # Number of instructions simulated
sim_seconds 1.958647 # Number of seconds simulated
@ -361,7 +361,7 @@ system.cpu0.kern.syscall::total 222 # nu
system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles
system.cpu0.numCycles 3916023774 # number of cpu cycles simulated
system.cpu0.num_insts 54072652 # Number of instructions executed
system.cpu0.num_refs 14919880 # Number of memory references
system.cpu0.num_refs 14724357 # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency
@ -692,7 +692,7 @@ system.cpu1.kern.syscall::total 104 # nu
system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles
system.cpu1.numCycles 3917294190 # number of cpu cycles simulated
system.cpu1.num_insts 5282991 # Number of instructions executed
system.cpu1.num_refs 1711037 # Number of memory references
system.cpu1.num_refs 1710778 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/home/stever/m5/m5_system_2.0b3/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -155,7 +155,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -175,7 +175,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -301,7 +301,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

15
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,13 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:15:41
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
M5 compiled Nov 2 2010 23:00:12
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 23:10:12
M5 executing on aus-bc2-b15
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1915548867000 because m5_exit instruction encountered

10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1445061 # Simulator instruction rate (inst/s)
host_mem_usage 277124 # Number of bytes of host memory used
host_seconds 38.85 # Real time elapsed on the host
host_tick_rate 49309117653 # Simulator tick rate (ticks/s)
host_inst_rate 1917155 # Simulator instruction rate (inst/s)
host_mem_usage 322176 # Number of bytes of host memory used
host_seconds 29.28 # Real time elapsed on the host
host_tick_rate 65417896896 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56137087 # Number of instructions simulated
sim_seconds 1.915549 # Number of seconds simulated
@ -342,7 +342,7 @@ system.cpu.kern.syscall::total 326 # nu
system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
system.cpu.numCycles 3831097734 # number of cpu cycles simulated
system.cpu.num_insts 56137087 # Number of instructions executed
system.cpu.num_refs 15658046 # Number of memory references
system.cpu.num_refs 15462519 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).

14
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
View file

@ -1,5 +1,9 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
exec filecode in scope
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, name, 'test.py'))
File "tests/quick/20.eio-short/test.py", line 29, in <module>
root.system.cpu.workload = EioProcess(file = binpath('anagram',
NameError: name 'EioProcess' is not defined

15
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,13 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:02:04
M5 executing on SC2B0619
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:33:04
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 250015500 because a thread reached the max instruction count

50
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -1,50 +0,0 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3013906 # Simulator instruction rate (inst/s)
host_mem_usage 181592 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_tick_rate 1504585693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 500032 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 500019 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 500032 # number of cpu cycles simulated
system.cpu.num_insts 500001 # Number of instructions executed
system.cpu.num_refs 182222 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------

14
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
View file

@ -1,5 +1,9 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
exec filecode in scope
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, name, 'test.py'))
File "tests/quick/20.eio-short/test.py", line 29, in <module>
root.system.cpu.workload = EioProcess(file = binpath('anagram',
NameError: name 'EioProcess' is not defined

17
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,13 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 19:15:13
M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
M5 started Aug 26 2010 19:20:56
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 727929000 because a thread reached the max instruction count
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:31:02
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing

233
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -1,233 +0,0 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1184343 # Simulator instruction rate (inst/s)
host_mem_usage 203180 # Number of bytes of host memory used
host_seconds 0.42 # Real time elapsed on the host
host_tick_rate 1723169900 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000728 # Number of seconds simulated
sim_ticks 727929000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.070111 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 180321 # number of overall hits
system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_misses 454 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.129371 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499617 # number of overall hits
system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_misses 403 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 500033 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 500020 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.014692 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 857 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1455858 # number of cpu cycles simulated
system.cpu.num_insts 500001 # Number of instructions executed
system.cpu.num_refs 182222 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------

20
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
View file

@ -1,11 +1,9 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
exec filecode in scope
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, name, 'test.py'))
File "tests/quick/30.eio-mp/test.py", line 29, in <module>
process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
NameError: name 'EioProcess' is not defined

23
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -1,3 +1,5 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -5,19 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 19:15:13
M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
M5 started Aug 26 2010 19:20:56
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 250015500 because a thread reached the max instruction count
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:31:02
M5 executing on aus-bc2-b15
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp

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