some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
src/arch/sparc/faults.cc: 1) s/Resumeable/Resumable/gc 2) s/if(/if (/gc 3) keep variables lowercase 4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv). src/arch/sparc/faults.hh: s/Resumeable/Resumable/ src/arch/sparc/isa_traits.hh: This is unused and unnecessary. src/arch/sparc/miscregfile.hh: add bitfield masks for some important ASRs (HPSTATE, PSTATE). --HG-- extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
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@ -240,7 +240,7 @@ template<> SparcFaultBase::FaultVals
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{"dev_mondo", 0x07D, 1611, {P, P, SH}};
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template<> SparcFaultBase::FaultVals
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SparcFault<ResumeableError>::vals =
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SparcFault<ResumableError>::vals =
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{"resume_error", 0x07E, 3330, {P, P, SH}};
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template<> SparcFaultBase::FaultVals
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@ -534,35 +534,35 @@ void SparcFaultBase::invoke(ThreadContext * tc)
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//We can refer to this to see what the trap level -was-, but something
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//in the middle could change it in the regfile out from under us.
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MiscReg TL = tc->readMiscReg(MISCREG_TL);
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MiscReg TT = tc->readMiscReg(MISCREG_TT);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg tl = tc->readMiscReg(MISCREG_TL);
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MiscReg tt = tc->readMiscReg(MISCREG_TT);
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MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
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Addr PC, NPC;
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PrivilegeLevel current;
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if(HPSTATE & (1 << 2))
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if (hpstate & HPSTATE::hpriv)
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current = Hyperprivileged;
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else if(PSTATE & (1 << 2))
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else if (pstate & PSTATE::priv)
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current = Privileged;
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else
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current = User;
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PrivilegeLevel level = getNextLevel(current);
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if(HPSTATE & (1 << 5) || TL == MaxTL - 1) {
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if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
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getREDVector(5, PC, NPC);
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doREDFault(tc, TT);
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doREDFault(tc, tt);
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//This changes the hpstate and pstate, so we need to make sure we
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//save the old version on the trap stack in doREDFault.
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enterREDState(tc);
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} else if(TL == MaxTL) {
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} else if (tl == MaxTL) {
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panic("Should go to error state here.. crap\n");
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//Do error_state somehow?
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//Probably inject a WDR fault using the interrupt mechanism.
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//What should the PC and NPC be set to?
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} else if(TL > MaxPTL && level == Privileged) {
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} else if (tl > MaxPTL && level == Privileged) {
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//guest_watchdog fault
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doNormalFault(tc, trapType(), true);
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getHyperVector(tc, PC, NPC, 2);
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@ -572,7 +572,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
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getHyperVector(tc, PC, NPC, trapType());
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} else {
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doNormalFault(tc, trapType(), false);
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getPrivVector(tc, PC, NPC, trapType(), TL+1);
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getPrivVector(tc, PC, NPC, trapType(), tl+1);
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}
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tc->setPC(PC);
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@ -210,7 +210,7 @@ class CpuMondo : public SparcFault<CpuMondo> {};
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class DevMondo : public SparcFault<DevMondo> {};
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class ResumeableError : public SparcFault<ResumeableError> {};
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class ResumableError : public SparcFault<ResumableError> {};
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class SpillNNormal : public EnumeratedFault<SpillNNormal>
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{
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@ -96,15 +96,6 @@ namespace SparcISA
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StaticInstPtr decodeInst(ExtMachInst);
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#if FULL_SYSTEM
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////////// Interrupt Stuff ///////////
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enum InterruptLevels
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{
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INTLEVEL_MIN = 1,
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INTLEVEL_MAX = 15,
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NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN
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};
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// I don't know what it's for, so I don't
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// know what SPARC's value should be
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// For loading... XXX This maybe could be USegEnd?? --ali
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@ -142,24 +142,26 @@ namespace SparcISA
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MISCREG_NUMMISCREGS
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};
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enum HPStateFields {
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id = 0x800, // this impl. dependent (id) field must always be '1' for T1000
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ibe = 0x400,
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red = 0x20,
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hpriv = 0x4,
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tlz = 0x1
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struct HPSTATE {
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const static uint64_t id = 0x800; // this impl. dependent (id) field m
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const static uint64_t ibe = 0x400;
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const static uint64_t red = 0x20;
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const static uint64_t hpriv = 0x4;
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const static uint64_t tlz = 0x1;
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};
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enum PStateFields {
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cle = 0x200,
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tle = 0x100,
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mm = 0xC0,
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pef = 0x10,
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am = 0x8,
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priv = 0x4,
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ie = 0x2
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struct PSTATE {
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const static int cle = 0x200;
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const static int tle = 0x100;
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const static int mm = 0xC0;
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const static int pef = 0x10;
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const static int am = 0x8;
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const static int priv = 0x4;
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const static int ie = 0x2;
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};
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const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
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const int NumMiscRegs = MISCREG_NUMMISCREGS;
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