ruby: MI_example updates to use the new config system
This commit is contained in:
Brad Beckmann
parent
502b8bd8a4
commit
b3d195153e
6 changed files with 185 additions and 70 deletions
128
configs/ruby/MI_example.py
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128
configs/ruby/MI_example.py
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@ -0,0 +1,128 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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#
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# Note: the cache latency is only used by the sequencer on fast path hits
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#
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class Cache(RubyCache):
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latency = 3
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def create_system(options, phys_mem, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MI_example':
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panic("This script requires the MI_example protocol to be built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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# Only one cache exists for this protocol, so by default use the L1D
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# config parameters.
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#
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cache = Cache(size = options.l1d_size,
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assoc = options.l1d_assoc)
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#
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# Only one unified L1 cache exists. Can cache instructions and data.
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#
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cpu_seq = RubySequencer(icache = cache,
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dcache = cache,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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cacheMemory = cache)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
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mem_module_size = phys_mem_size / options.num_dirs
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(version = i)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size),
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memBuffer = mem_cntrl)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_device in enumerate(dma_devices):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
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return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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@ -33,6 +33,7 @@ from m5.defines import buildEnv
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from m5.util import addToPath
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import MOESI_hammer
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import MI_example
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def create_system(options, physmem, piobus = None, dma_devices = []):
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@ -44,6 +45,12 @@ def create_system(options, physmem, piobus = None, dma_devices = []):
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physmem, \
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piobus, \
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dma_devices)
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elif protocol == "MI_example":
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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MI_example.create_system(options, \
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physmem, \
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piobus, \
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dma_devices)
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else:
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print "Error: unsupported ruby protocol"
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sys.exit(1)
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@ -1,7 +1,9 @@
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machine(L1Cache, "MI Example L1 Cache")
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: int cache_response_latency,
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int issue_latency
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: Sequencer * sequencer,
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CacheMemory * cacheMemory,
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int cache_response_latency = 12,
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int issue_latency = 2
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{
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// NETWORK BUFFERS
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@ -44,7 +46,6 @@ machine(L1Cache, "MI Example L1 Cache")
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// STRUCTURE DEFINITIONS
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MessageBuffer mandatoryQueue, ordered="false";
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Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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@ -54,17 +55,6 @@ machine(L1Cache, "MI Example L1 Cache")
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address, Entry);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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void profileMiss(CacheMsg);
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}
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// TBE fields
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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@ -81,8 +71,6 @@ machine(L1Cache, "MI Example L1 Cache")
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// STRUCTURES
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CacheMemory cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
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TBETable TBEs, template_hack="<L1Cache_TBE>";
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@ -100,6 +88,9 @@ machine(L1Cache, "MI Example L1 Cache")
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}
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}
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Entry getCacheEntry(Address addr), return_by_ref="yes" {
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return static_cast(Entry, cacheMemory[addr]);
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}
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State getState(Address addr) {
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@ -107,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache")
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return TBEs[addr].TBEState;
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}
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else if (cacheMemory.isTagPresent(addr)) {
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return cacheMemory[addr].CacheState;
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return getCacheEntry(addr).CacheState;
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}
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else {
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return State:I;
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@ -121,7 +112,7 @@ machine(L1Cache, "MI Example L1 Cache")
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}
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if (cacheMemory.isTagPresent(addr)) {
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cacheMemory[addr].CacheState := state;
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getCacheEntry(addr).CacheState := state;
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if (state == State:M) {
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cacheMemory.changePermission(addr, AccessPermission:Read_Write);
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} else {
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@ -207,7 +198,7 @@ machine(L1Cache, "MI Example L1 Cache")
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out_msg.Type := CoherenceRequestType:PUTX;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.DataBlk := cacheMemory[address].DataBlk;
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out_msg.DataBlk := getCacheEntry(address).DataBlk;
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out_msg.MessageSize := MessageSizeType:Data;
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}
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}
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@ -220,7 +211,7 @@ machine(L1Cache, "MI Example L1 Cache")
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := cacheMemory[address].DataBlk;
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out_msg.DataBlk := getCacheEntry(address).DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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@ -271,19 +262,19 @@ machine(L1Cache, "MI Example L1 Cache")
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}
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action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
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DEBUG_EXPR(cacheMemory[address].DataBlk);
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sequencer.readCallback(address, cacheMemory[address].DataBlk);
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DEBUG_EXPR(getCacheEntry(address).DataBlk);
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sequencer.readCallback(address, getCacheEntry(address).DataBlk);
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}
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action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
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DEBUG_EXPR(cacheMemory[address].DataBlk);
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sequencer.writeCallback(address, cacheMemory[address].DataBlk);
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DEBUG_EXPR(getCacheEntry(address).DataBlk);
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sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
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}
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action(u_writeDataToCache, "u", desc="Write data to the cache") {
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peek(responseNetwork_in, ResponseMsg) {
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cacheMemory[address].DataBlk := in_msg.DataBlk;
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getCacheEntry(address).DataBlk := in_msg.DataBlk;
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}
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}
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@ -298,7 +289,7 @@ machine(L1Cache, "MI Example L1 Cache")
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}
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action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
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TBEs[address].DataBlk := cacheMemory[address].DataBlk;
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TBEs[address].DataBlk := getCacheEntry(address).DataBlk;
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}
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action(z_stall, "z", desc="stall") {
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@ -1,6 +1,8 @@
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machine(Directory, "Directory protocol")
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: int directory_latency
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: DirectoryMemory * directory,
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MemoryControl * memBuffer,
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int directory_latency = 12
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{
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MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
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@ -48,24 +50,13 @@ machine(Directory, "Directory protocol")
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...") {
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structure(Entry, desc="...", interface="AbstractEntry") {
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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NetDest Sharers, desc="Sharers for this block";
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NetDest Owner, desc="Owner of this block";
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}
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external_type(DirectoryMemory) {
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Entry lookup(Address);
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bool isPresent(Address);
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void invalidateBlock(Address);
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}
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external_type(MemoryControl, inport="yes", outport="yes") {
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}
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// TBE entries for DMA requests
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structure(TBE, desc="TBE entries for outstanding DMA requests") {
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Address PhysicalAddress, desc="physical address";
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@ -83,17 +74,17 @@ machine(Directory, "Directory protocol")
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}
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// ** OBJECTS **
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DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory"])';
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MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_control"])';
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TBETable TBEs, template_hack="<Directory_TBE>";
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Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
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return static_cast(Entry, directory[addr]);
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}
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State getState(Address addr) {
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if (TBEs.isPresent(addr)) {
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return TBEs[addr].TBEState;
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} else if (directory.isPresent(addr)) {
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return directory[addr].DirectoryState;
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return getDirectoryEntry(addr).DirectoryState;
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} else {
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return State:I;
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}
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@ -108,14 +99,14 @@ machine(Directory, "Directory protocol")
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if (directory.isPresent(addr)) {
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if (state == State:I) {
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assert(directory[addr].Owner.count() == 0);
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assert(directory[addr].Sharers.count() == 0);
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assert(getDirectoryEntry(addr).Owner.count() == 0);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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} else if (state == State:M) {
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assert(directory[addr].Owner.count() == 1);
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assert(directory[addr].Sharers.count() == 0);
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assert(getDirectoryEntry(addr).Owner.count() == 1);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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}
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directory[addr].DirectoryState := state;
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getDirectoryEntry(addr).DirectoryState := state;
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}
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}
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@ -151,7 +142,7 @@ machine(Directory, "Directory protocol")
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} else if (in_msg.Type == CoherenceRequestType:GETX) {
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trigger(Event:GETX, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:PUTX) {
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if (directory[in_msg.Address].Owner.isElement(in_msg.Requestor)) {
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if (getDirectoryEntry(in_msg.Address).Owner.isElement(in_msg.Requestor)) {
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trigger(Event:PUTX, in_msg.Address);
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} else {
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trigger(Event:PUTX_NotOwner, in_msg.Address);
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@ -219,7 +210,7 @@ machine(Directory, "Directory protocol")
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}
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action(c_clearOwner, "c", desc="Clear the owner field") {
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directory[address].Owner.clear();
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getDirectoryEntry(address).Owner.clear();
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}
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action(d_sendData, "d", desc="Send data to requestor") {
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@ -279,22 +270,22 @@ machine(Directory, "Directory protocol")
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action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
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peek(requestQueue_in, RequestMsg) {
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directory[address].Owner.clear();
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directory[address].Owner.add(in_msg.Requestor);
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getDirectoryEntry(address).Owner.clear();
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getDirectoryEntry(address).Owner.add(in_msg.Requestor);
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}
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}
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action(f_forwardRequest, "f", desc="Forward request to owner") {
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peek(requestQueue_in, RequestMsg) {
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APPEND_TRANSITION_COMMENT("Own: ");
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APPEND_TRANSITION_COMMENT(directory[in_msg.Address].Owner);
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APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Address).Owner);
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APPEND_TRANSITION_COMMENT("Req: ");
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APPEND_TRANSITION_COMMENT(in_msg.Requestor);
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enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Type := in_msg.Type;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination := directory[in_msg.Address].Owner;
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out_msg.Destination := getDirectoryEntry(in_msg.Address).Owner;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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@ -306,7 +297,7 @@ machine(Directory, "Directory protocol")
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:INV;
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out_msg.Requestor := machineID;
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out_msg.Destination := directory[in_msg.PhysicalAddress].Owner;
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out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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@ -324,13 +315,13 @@ machine(Directory, "Directory protocol")
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peek(requestQueue_in, RequestMsg) {
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// assert(in_msg.Dirty);
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// assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
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directory[in_msg.Address].DataBlk := in_msg.DataBlk;
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//directory[in_msg.Address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
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getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
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//getDirectoryEntry(in_msg.Address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
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}
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}
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action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
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directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
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getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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@ -378,7 +369,7 @@ machine(Directory, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Requestor;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := directory[in_msg.Address].DataBlk;
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out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
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DEBUG_EXPR(out_msg);
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}
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}
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@ -392,7 +383,7 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Sender := machineID;
|
||||
//out_msg.OriginalRequestorMachId := machineID;
|
||||
out_msg.MessageSize := in_msg.MessageSize;
|
||||
out_msg.DataBlk := directory[address].DataBlk;
|
||||
out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
|
||||
DEBUG_EXPR(out_msg);
|
||||
}
|
||||
}
|
||||
|
|
@ -453,8 +444,10 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
|
||||
action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") {
|
||||
//directory[address].DataBlk := TBEs[address].DataBlk;
|
||||
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
|
||||
//getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
|
||||
getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk,
|
||||
addressOffset(TBEs[address].PhysicalAddress),
|
||||
TBEs[address].Len);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
|
||||
machine(DMA, "DMA Controller")
|
||||
: int request_latency
|
||||
: DMASequencer * dma_sequencer,
|
||||
int request_latency
|
||||
{
|
||||
|
||||
MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true";
|
||||
|
|
@ -19,13 +20,7 @@ machine(DMA, "DMA Controller")
|
|||
Ack, desc="DMA write to memory completed";
|
||||
}
|
||||
|
||||
external_type(DMASequencer) {
|
||||
void ackCallback();
|
||||
void dataCallback(DataBlock);
|
||||
}
|
||||
|
||||
MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
|
||||
DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
|
||||
State cur_state, no_vector="true";
|
||||
|
||||
State getState(Address addr) {
|
||||
|
|
|
|||
|
|
@ -103,6 +103,7 @@ external_type(AbstractEntry, primitive="yes");
|
|||
external_type(DirectoryMemory) {
|
||||
AbstractEntry lookup(Address);
|
||||
bool isPresent(Address);
|
||||
void invalidateBlock(Address);
|
||||
}
|
||||
|
||||
external_type(AbstractCacheEntry, primitive="yes");
|
||||
|
|
|
|||
Loading…
Reference in a new issue