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--HG--
extra : convert_revision : dadfa2cd97908d769f1e2d5c645140f296ec6a82
This commit is contained in:
Steve Reinhardt 2004-04-02 23:19:08 -08:00
commit b3b0a4705b
8 changed files with 56 additions and 66 deletions
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78
arch/alpha/alpha_memory.cc
View file

@ -44,14 +44,14 @@ using namespace std;
// //
// Alpha TLB // Alpha TLB
// //
AlphaTlb::AlphaTlb(const string &name, int s) AlphaTLB::AlphaTLB(const string &name, int s)
: SimObject(name), size(s), nlu(0) : SimObject(name), size(s), nlu(0)
{ {
table = new AlphaISA::PTE[size]; table = new AlphaISA::PTE[size];
memset(table, 0, sizeof(AlphaISA::PTE[size])); memset(table, 0, sizeof(AlphaISA::PTE[size]));
} }
AlphaTlb::~AlphaTlb() AlphaTLB::~AlphaTLB()
{ {
if (table) if (table)
delete [] table; delete [] table;
@ -59,7 +59,7 @@ AlphaTlb::~AlphaTlb()
// look up an entry in the TLB // look up an entry in the TLB
AlphaISA::PTE * AlphaISA::PTE *
AlphaTlb::lookup(Addr vpn, uint8_t asn) const AlphaTLB::lookup(Addr vpn, uint8_t asn) const
{ {
DPRINTF(TLB, "lookup %#x\n", vpn); DPRINTF(TLB, "lookup %#x\n", vpn);
@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
void void
AlphaTlb::checkCacheability(MemReqPtr &req) AlphaTLB::checkCacheability(MemReqPtr &req)
{ {
// in Alpha, cacheability is controlled by upper-level bits of the // in Alpha, cacheability is controlled by upper-level bits of the
// physical address // physical address
@ -111,7 +111,7 @@ AlphaTlb::checkCacheability(MemReqPtr &req)
// insert a new TLB entry // insert a new TLB entry
void void
AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte) AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte)
{ {
if (table[nlu].valid) { if (table[nlu].valid) {
Addr oldvpn = table[nlu].tag; Addr oldvpn = table[nlu].tag;
@ -145,7 +145,7 @@ AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte)
} }
void void
AlphaTlb::flushAll() AlphaTLB::flushAll()
{ {
memset(table, 0, sizeof(AlphaISA::PTE[size])); memset(table, 0, sizeof(AlphaISA::PTE[size]));
lookupTable.clear(); lookupTable.clear();
@ -153,7 +153,7 @@ AlphaTlb::flushAll()
} }
void void
AlphaTlb::flushProcesses() AlphaTLB::flushProcesses()
{ {
PageTable::iterator i = lookupTable.begin(); PageTable::iterator i = lookupTable.begin();
PageTable::iterator end = lookupTable.end(); PageTable::iterator end = lookupTable.end();
@ -173,7 +173,7 @@ AlphaTlb::flushProcesses()
} }
void void
AlphaTlb::flushAddr(Addr vaddr, uint8_t asn) AlphaTLB::flushAddr(Addr vaddr, uint8_t asn)
{ {
Addr vpn = VA_VPN(vaddr); Addr vpn = VA_VPN(vaddr);
@ -201,7 +201,7 @@ AlphaTlb::flushAddr(Addr vaddr, uint8_t asn)
void void
AlphaTlb::serialize(ostream &os) AlphaTLB::serialize(ostream &os)
{ {
SERIALIZE_SCALAR(size); SERIALIZE_SCALAR(size);
SERIALIZE_SCALAR(nlu); SERIALIZE_SCALAR(nlu);
@ -213,7 +213,7 @@ AlphaTlb::serialize(ostream &os)
} }
void void
AlphaTlb::unserialize(Checkpoint *cp, const string &section) AlphaTLB::unserialize(Checkpoint *cp, const string &section)
{ {
UNSERIALIZE_SCALAR(size); UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(nlu); UNSERIALIZE_SCALAR(nlu);
@ -231,13 +231,13 @@ AlphaTlb::unserialize(Checkpoint *cp, const string &section)
// //
// Alpha ITB // Alpha ITB
// //
AlphaItb::AlphaItb(const std::string &name, int size) AlphaITB::AlphaITB(const std::string &name, int size)
: AlphaTlb(name, size) : AlphaTLB(name, size)
{} {}
void void
AlphaItb::regStats() AlphaITB::regStats()
{ {
hits hits
.name(name() + ".hits") .name(name() + ".hits")
@ -256,7 +256,7 @@ AlphaItb::regStats()
} }
void void
AlphaItb::fault(Addr pc, ExecContext *xc) const AlphaITB::fault(Addr pc, ExecContext *xc) const
{ {
uint64_t *ipr = xc->regs.ipr; uint64_t *ipr = xc->regs.ipr;
@ -269,7 +269,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
Fault Fault
AlphaItb::translate(MemReqPtr &req) const AlphaITB::translate(MemReqPtr &req) const
{ {
InternalProcReg *ipr = req->xc->regs.ipr; InternalProcReg *ipr = req->xc->regs.ipr;
@ -287,7 +287,7 @@ AlphaItb::translate(MemReqPtr &req) const
if (!validVirtualAddress(req->vaddr)) { if (!validVirtualAddress(req->vaddr)) {
fault(req->vaddr, req->xc); fault(req->vaddr, req->xc);
acv++; acv++;
return Itb_Acv_Fault; return ITB_Acv_Fault;
} }
// Check for "superpage" mapping: when SP<1> is set, and // Check for "superpage" mapping: when SP<1> is set, and
@ -299,7 +299,7 @@ AlphaItb::translate(MemReqPtr &req) const
if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
fault(req->vaddr, req->xc); fault(req->vaddr, req->xc);
acv++; acv++;
return Itb_Acv_Fault; return ITB_Acv_Fault;
} }
req->paddr = req->vaddr & PA_IMPL_MASK; req->paddr = req->vaddr & PA_IMPL_MASK;
@ -311,7 +311,7 @@ AlphaItb::translate(MemReqPtr &req) const
if (!pte) { if (!pte) {
fault(req->vaddr, req->xc); fault(req->vaddr, req->xc);
misses++; misses++;
return Itb_Fault_Fault; return ITB_Fault_Fault;
} }
req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3); req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3);
@ -321,7 +321,7 @@ AlphaItb::translate(MemReqPtr &req) const
// instruction access fault // instruction access fault
fault(req->vaddr, req->xc); fault(req->vaddr, req->xc);
acv++; acv++;
return Itb_Acv_Fault; return ITB_Acv_Fault;
} }
hits++; hits++;
@ -341,12 +341,12 @@ AlphaItb::translate(MemReqPtr &req) const
// //
// Alpha DTB // Alpha DTB
// //
AlphaDtb::AlphaDtb(const std::string &name, int size) AlphaDTB::AlphaDTB(const std::string &name, int size)
: AlphaTlb(name, size) : AlphaTLB(name, size)
{} {}
void void
AlphaDtb::regStats() AlphaDTB::regStats()
{ {
read_hits read_hits
.name(name() + ".read_hits") .name(name() + ".read_hits")
@ -415,7 +415,7 @@ AlphaDtb::regStats()
} }
void void
AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
{ {
uint64_t *ipr = xc->regs.ipr; uint64_t *ipr = xc->regs.ipr;
@ -439,7 +439,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
} }
Fault Fault
AlphaDtb::translate(MemReqPtr &req, bool write) const AlphaDTB::translate(MemReqPtr &req, bool write) const
{ {
RegFile *regs = &req->xc->regs; RegFile *regs = &req->xc->regs;
Addr pc = regs->pc; Addr pc = regs->pc;
@ -553,7 +553,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
} }
AlphaISA::PTE & AlphaISA::PTE &
AlphaTlb::index(bool advance) AlphaTLB::index(bool advance)
{ {
AlphaISA::PTE *pte = &table[nlu]; AlphaISA::PTE *pte = &table[nlu];
@ -563,43 +563,43 @@ AlphaTlb::index(bool advance)
return *pte; return *pte;
} }
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb) BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
Param<int> size; Param<int> size;
END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb) END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb) BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
INIT_PARAM_DFLT(size, "TLB size", 48) INIT_PARAM_DFLT(size, "TLB size", 48)
END_INIT_SIM_OBJECT_PARAMS(AlphaItb) END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
CREATE_SIM_OBJECT(AlphaItb) CREATE_SIM_OBJECT(AlphaITB)
{ {
return new AlphaItb(getInstanceName(), size); return new AlphaITB(getInstanceName(), size);
} }
REGISTER_SIM_OBJECT("AlphaITB", AlphaItb) REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb) BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
Param<int> size; Param<int> size;
END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb) END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb) BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
INIT_PARAM_DFLT(size, "TLB size", 64) INIT_PARAM_DFLT(size, "TLB size", 64)
END_INIT_SIM_OBJECT_PARAMS(AlphaDtb) END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
CREATE_SIM_OBJECT(AlphaDtb) CREATE_SIM_OBJECT(AlphaDTB)
{ {
return new AlphaDtb(getInstanceName(), size); return new AlphaDTB(getInstanceName(), size);
} }
REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb) REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)

14
arch/alpha/alpha_memory.hh
View file

@ -37,7 +37,7 @@
class ExecContext; class ExecContext;
class AlphaTlb : public SimObject class AlphaTLB : public SimObject
{ {
protected: protected:
typedef std::multimap<Addr, int> PageTable; typedef std::multimap<Addr, int> PageTable;
@ -51,8 +51,8 @@ class AlphaTlb : public SimObject
AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const; AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
public: public:
AlphaTlb(const std::string &name, int size); AlphaTLB(const std::string &name, int size);
virtual ~AlphaTlb(); virtual ~AlphaTLB();
int getsize() const { return size; } int getsize() const { return size; }
@ -77,7 +77,7 @@ class AlphaTlb : public SimObject
virtual void unserialize(Checkpoint *cp, const std::string &section); virtual void unserialize(Checkpoint *cp, const std::string &section);
}; };
class AlphaItb : public AlphaTlb class AlphaITB : public AlphaTLB
{ {
protected: protected:
mutable Statistics::Scalar<> hits; mutable Statistics::Scalar<> hits;
@ -89,13 +89,13 @@ class AlphaItb : public AlphaTlb
void fault(Addr pc, ExecContext *xc) const; void fault(Addr pc, ExecContext *xc) const;
public: public:
AlphaItb(const std::string &name, int size); AlphaITB(const std::string &name, int size);
virtual void regStats(); virtual void regStats();
Fault translate(MemReqPtr &req) const; Fault translate(MemReqPtr &req) const;
}; };
class AlphaDtb : public AlphaTlb class AlphaDTB : public AlphaTLB
{ {
protected: protected:
mutable Statistics::Scalar<> read_hits; mutable Statistics::Scalar<> read_hits;
@ -115,7 +115,7 @@ class AlphaDtb : public AlphaTlb
void fault(Addr pc, uint64_t flags, ExecContext *xc) const; void fault(Addr pc, uint64_t flags, ExecContext *xc) const;
public: public:
AlphaDtb(const std::string &name, int size); AlphaDTB(const std::string &name, int size);
virtual void regStats(); virtual void regStats();
Fault translate(MemReqPtr &req, bool write) const; Fault translate(MemReqPtr &req, bool write) const;

6
cpu/base_cpu.cc
View file

@ -237,10 +237,4 @@ BaseCPU::clear_interrupts()
#endif // FULL_SYSTEM #endif // FULL_SYSTEM
//
// This declaration is not needed now that SamplingCPU provides a
// BaseCPUBuilder object.
//
#if 0
DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
#endif

12
cpu/simple_cpu/simple_cpu.cc
View file

@ -116,7 +116,7 @@ SimpleCPU::SimpleCPU(const string &_name,
Counter max_insts_all_threads, Counter max_insts_all_threads,
Counter max_loads_any_thread, Counter max_loads_any_thread,
Counter max_loads_all_threads, Counter max_loads_all_threads,
AlphaItb *itb, AlphaDtb *dtb, AlphaITB *itb, AlphaDTB *dtb,
FunctionalMemory *mem, FunctionalMemory *mem,
MemInterface *icache_interface, MemInterface *icache_interface,
MemInterface *dcache_interface, MemInterface *dcache_interface,
@ -778,8 +778,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<Counter> max_loads_all_threads; Param<Counter> max_loads_all_threads;
#ifdef FULL_SYSTEM #ifdef FULL_SYSTEM
SimObjectParam<AlphaItb *> itb; SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDtb *> dtb; SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<FunctionalMemory *> mem; SimObjectParam<FunctionalMemory *> mem;
SimObjectParam<System *> system; SimObjectParam<System *> system;
Param<int> mult; Param<int> mult;
@ -852,11 +852,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
defer_registration); defer_registration);
#endif // FULL_SYSTEM #endif // FULL_SYSTEM
#if 0
if (!defer_registration) {
cpu->registerExecContexts();
}
#endif
return cpu; return cpu;
} }

4
dev/ethertap.cc
View file

@ -313,8 +313,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
SimObjectParam<EtherInt *> peer; SimObjectParam<EtherInt *> peer;
SimObjectParam<EtherDump *> packet_dump; SimObjectParam<EtherDump *> packet_dump;
Param<uint16_t> port; Param<unsigned> port;
Param<uint16_t> bufsz; Param<unsigned> bufsz;
END_DECLARE_SIM_OBJECT_PARAMS(EtherTap) END_DECLARE_SIM_OBJECT_PARAMS(EtherTap)

2
kern/tru64/tru64_system.cc
View file

@ -304,7 +304,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
Param<bool> bin; Param<bool> bin;
SimObjectParam<MemoryController *> mem_ctl; SimObjectParam<MemoryController *> mem_ctl;
SimObjectParam<PhysicalMemory *> physmem; SimObjectParam<PhysicalMemory *> physmem;
Param<uint64_t> init_param; Param<unsigned int> init_param;
Param<string> kernel_code; Param<string> kernel_code;
Param<string> console_code; Param<string> console_code;

2
sim/process.cc
View file

@ -221,7 +221,7 @@ Process::sim_fd(int tgt_fd)
// that can be constructed (i.e., no REGISTER_SIM_OBJECT() macro call, // that can be constructed (i.e., no REGISTER_SIM_OBJECT() macro call,
// which is where these get declared for concrete types). // which is where these get declared for concrete types).
// //
DEFINE_SIM_OBJECT_CLASS_NAME("Process object", Process) DEFINE_SIM_OBJECT_CLASS_NAME("Process", Process)
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////

4
test/paramtest.cc
View file

@ -57,8 +57,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(ParamTest)
VectorParam<string> vecstring; VectorParam<string> vecstring;
Param<bool> boolparam; Param<bool> boolparam;
VectorParam<bool> vecbool; VectorParam<bool> vecbool;
SimObjectParam<mem_hierarchy_obj *> memobj; SimObjectParam<BaseMemory *> memobj;
SimObjectVectorParam<mem_hierarchy_obj *> vecmemobj; SimObjectVectorParam<BaseMemory *> vecmemobj;
SimpleEnumParam<Enum1Type> enum1; SimpleEnumParam<Enum1Type> enum1;
MappedEnumParam<Enum2Type> enum2; MappedEnumParam<Enum2Type> enum2;
SimpleEnumVectorParam<Enum1Type> vecenum1; SimpleEnumVectorParam<Enum1Type> vecenum1;