Implement a very very simple bus
requestTime -> time responseTime -> packet.time Make CPU and memory able to connect to the bus dev/io_device.cc: update for request and packet both having a time hand platform off to port for eventual selection of request modes dev/io_device.hh: update for request and packet both havig a time hand platform off to port for eventual selection of request modes mem/bus.hh: Add a device map struct that maps a range to a portId - Which needs work it theory it should be an interval tree - but it is a list and works fine right now Add a function called findPort which returns port for an addr range Add a deviceBlockSize function that really shouldn't exist, but it was easier than fixing the translating port mem/packet.hh: add a time to each packet mem/physical.cc: mem/physical.hh: python/m5/objects/PhysicalMemory.py: Make physical memory take a MemObject parameter of what to connect to mem/request.hh: remove requestTime/responseTime for just time in request which is requset time and the time in the packet which is responsetime python/m5/objects/BaseCPU.py: Instead of memory cpu connects to any memory object python/m5/objects/Bus.py: Fix for new bus object --HG-- extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
This commit is contained in:
parent
a70ce910f3
commit
b38f67d5b7
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@ -30,8 +30,8 @@
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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PioPort::PioPort(PioDevice *dev)
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PioPort::PioPort(PioDevice *dev, Platform *p)
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: device(dev)
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: device(dev), platform(p)
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{ }
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{ }
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@ -75,7 +75,7 @@ PioPort::SendEvent::process()
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PioDevice::PioDevice(const std::string &name, Platform *p)
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PioDevice::PioDevice(const std::string &name, Platform *p)
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: SimObject(name), platform(p)
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: SimObject(name), platform(p)
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{
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{
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pioPort = new PioPort(this);
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pioPort = new PioPort(this, p);
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}
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}
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@ -83,7 +83,7 @@ bool
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PioPort::recvTiming(Packet &pkt)
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PioPort::recvTiming(Packet &pkt)
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{
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{
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device->recvAtomic(pkt);
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device->recvAtomic(pkt);
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sendTiming(pkt, pkt.req->responseTime-pkt.req->requestTime);
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sendTiming(pkt, pkt.time-pkt.req->time);
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return Success;
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return Success;
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}
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}
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@ -148,7 +148,7 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
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basePkt.result = Unknown;
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basePkt.result = Unknown;
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basePkt.req = NULL;
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basePkt.req = NULL;
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baseReq.nicReq = true;
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baseReq.nicReq = true;
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baseReq.requestTime = curTick;
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baseReq.time = curTick;
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completionEvent = event;
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completionEvent = event;
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@ -183,7 +183,7 @@ DmaPort::sendDma(Packet &pkt)
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transmitList.push_back(&packet);
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transmitList.push_back(&packet);
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} else if (state == Atomic) {*/
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} else if (state == Atomic) {*/
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sendAtomic(pkt);
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sendAtomic(pkt);
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completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime);
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completionEvent->schedule(pkt.time - pkt.req->time);
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completionEvent = NULL;
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completionEvent = NULL;
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/* } else if (state == Functional) {
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/* } else if (state == Functional) {
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sendFunctional(pkt);
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sendFunctional(pkt);
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@ -57,7 +57,7 @@ class PioPort : public Port
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/** The platform that device/port are in. This is used to select which mode
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/** The platform that device/port are in. This is used to select which mode
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* we are currently operating in. */
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* we are currently operating in. */
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Platfrom *platform;
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Platform *platform;
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/** A list of outgoing timing response packets that haven't been serviced
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/** A list of outgoing timing response packets that haven't been serviced
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* yet. */
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* yet. */
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127
mem/bus.cc
Normal file
127
mem/bus.cc
Normal file
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@ -0,0 +1,127 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Definition of a bus object.
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*/
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#include "bus.hh"
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#include "sim/builder.hh"
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/** Function called by the port when the bus is recieving a Timing
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* transaction.*/
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bool
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Bus::recvTiming(Packet &pkt, int id)
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{
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panic("I need to be implemented, but not right now.");
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}
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Port *
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Bus::findPort(Addr addr, int id)
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{
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/* An interval tree would be a better way to do this. --ali. */
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int dest_id = -1;
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int i = 0;
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bool found = false;
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while (i < portList.size() && !found)
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{
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if (portList[i].range == addr) {
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dest_id = portList[i].portId;
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found = true;
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}
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}
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assert(dest_id != -1 && "Unable to find destination");
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// we shouldn't be sending this back to where it came from
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assert(dest_id != id);
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return interfaces[dest_id];
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}
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/** Function called by the port when the bus is recieving a Atomic
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* transaction.*/
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Tick
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Bus::recvAtomic(Packet &pkt, int id)
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{
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return findPort(pkt.addr, id)->sendAtomic(pkt);
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}
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/** Function called by the port when the bus is recieving a Functional
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* transaction.*/
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void
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Bus::recvFunctional(Packet &pkt, int id)
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{
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findPort(pkt.addr, id)->sendFunctional(pkt);
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}
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/** Function called by the port when the bus is recieving a status change.*/
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void
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Bus::recvStatusChange(Port::Status status, int id)
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{
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assert(status == Port:: RangeChange &&
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"The other statuses need to be implemented.");
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Port *port = interfaces[id];
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AddrRangeList ranges;
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bool owner;
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port->getPeerAddressRanges(ranges, owner);
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// not dealing with snooping yet either
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assert(owner == true);
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// or multiple ranges
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assert(ranges.size() == 1);
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DevMap dm;
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dm.portId = id;
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dm.range = ranges.front();
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portList.push_back(dm);
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}
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void
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Bus::BusPort::addressRanges(AddrRangeList &range_list, bool &owner)
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{
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panic("I'm not implemented.\n");
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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Param<int> bus_id;
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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INIT_PARAM(bus_id, "junk bus id")
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END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
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CREATE_SIM_OBJECT(Bus)
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{
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return new Bus(getInstanceName());
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}
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REGISTER_SIM_OBJECT("Bus", Bus)
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24
mem/bus.hh
24
mem/bus.hh
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class Bus : public MemObject
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class Bus : public MemObject
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{
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{
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struct DevMap {
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int portId;
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Range<Addr> range;
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};
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std::vector<DevMap> portList;
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/** Function called by the port when the bus is recieving a Timing
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/** Function called by the port when the bus is recieving a Timing
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transaction.*/
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transaction.*/
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bool recvTiming(Packet &pkt, int id);
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bool recvTiming(Packet &pkt, int id);
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@ -60,6 +67,16 @@ class Bus : public MemObject
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/** Function called by the port when the bus is recieving a status change.*/
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/** Function called by the port when the bus is recieving a status change.*/
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void recvStatusChange(Port::Status status, int id);
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void recvStatusChange(Port::Status status, int id);
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/** Find which port connected to this bus (if any) should be given a packet
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* with this address.
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* @param addr Address to find port for.
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* @param id Id of the port this packet was received from (to prevent
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* loops)
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* @return pointer to port that the packet should be sent out of.
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*/
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Port *
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Bus::findPort(Addr addr, int id);
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/** Decleration of the buses port type, one will be instantiated for each
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/** Decleration of the buses port type, one will be instantiated for each
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of the interfaces connecting to the bus. */
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of the interfaces connecting to the bus. */
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class BusPort : public Port
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class BusPort : public Port
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@ -104,6 +121,10 @@ class Bus : public MemObject
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// the 'owned' address ranges of all the other interfaces on
|
// the 'owned' address ranges of all the other interfaces on
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// this bus...
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// this bus...
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virtual void addressRanges(AddrRangeList &range_list, bool &owner);
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virtual void addressRanges(AddrRangeList &range_list, bool &owner);
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|
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// Hack to make translating port work without changes
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virtual int deviceBlockSize() { return 32; }
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|
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};
|
};
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/** A count of the number of interfaces connected to this bus. */
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/** A count of the number of interfaces connected to this bus. */
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@ -123,6 +144,9 @@ class Bus : public MemObject
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interfaces[id] = new BusPort(this, id);
|
interfaces[id] = new BusPort(this, id);
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return interfaces[id];
|
return interfaces[id];
|
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}
|
}
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|
Bus(const std::string &n)
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|
: MemObject(n) {}
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|
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};
|
};
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|
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#endif //__MEM_BUS_HH__
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#endif //__MEM_BUS_HH__
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|
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|
@ -112,6 +112,9 @@ struct Packet
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/** The command of the transaction. */
|
/** The command of the transaction. */
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Command cmd;
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Command cmd;
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|
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|
/** The time this request was responded to. Used to calculate latencies. */
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|
Tick time;
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|
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/** The result of the packet transaction. */
|
/** The result of the packet transaction. */
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PacketResult result;
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PacketResult result;
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|
|
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|
|
|
@ -69,8 +69,8 @@ PhysicalMemory::MemResponseEvent::description()
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return "Physical Memory Timing Access respnse event";
|
return "Physical Memory Timing Access respnse event";
|
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}
|
}
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|
|
||||||
PhysicalMemory::PhysicalMemory(const string &n)
|
PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus)
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: MemObject(n), base_addr(0), pmem_addr(NULL)
|
: MemObject(n), memPort(this), base_addr(0), pmem_addr(NULL)
|
||||||
{
|
{
|
||||||
// Hardcoded to 128 MB for now.
|
// Hardcoded to 128 MB for now.
|
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pmem_size = 1 << 27;
|
pmem_size = 1 << 27;
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|
@ -88,6 +88,14 @@ PhysicalMemory::PhysicalMemory(const string &n)
|
||||||
}
|
}
|
||||||
|
|
||||||
page_ptr = 0;
|
page_ptr = 0;
|
||||||
|
|
||||||
|
Port *peer_port;
|
||||||
|
peer_port = bus->getPort();
|
||||||
|
memPort.setPeer(peer_port);
|
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|
peer_port->setPeer(&memPort);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
PhysicalMemory::~PhysicalMemory()
|
PhysicalMemory::~PhysicalMemory()
|
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|
@ -181,7 +189,15 @@ void
|
||||||
PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
|
PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
|
||||||
bool &owner)
|
bool &owner)
|
||||||
{
|
{
|
||||||
panic("??");
|
memory->getAddressRanges(range_list, owner);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
PhysicalMemory::getAddressRanges(AddrRangeList &range_list, bool &owner)
|
||||||
|
{
|
||||||
|
owner = true;
|
||||||
|
range_list.clear();
|
||||||
|
range_list.push_back(RangeSize(base_addr, pmem_size));
|
||||||
}
|
}
|
||||||
|
|
||||||
int
|
int
|
||||||
|
@ -325,6 +341,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
#endif
|
#endif
|
||||||
Param<Range<Addr> > range;
|
Param<Range<Addr> > range;
|
||||||
|
SimObjectParam<MemObject*> bus;
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
|
END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
|
||||||
|
|
||||||
|
@ -334,7 +351,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
#endif
|
#endif
|
||||||
INIT_PARAM(range, "Device Address Range")
|
INIT_PARAM(range, "Device Address Range"),
|
||||||
|
INIT_PARAM(bus, "bus object memory connects to")
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
|
END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
|
||||||
|
|
||||||
|
@ -346,7 +364,7 @@ CREATE_SIM_OBJECT(PhysicalMemory)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return new PhysicalMemory(getInstanceName());
|
return new PhysicalMemory(getInstanceName(), bus);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)
|
REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)
|
||||||
|
|
|
@ -69,6 +69,8 @@ class PhysicalMemory : public MemObject
|
||||||
virtual int deviceBlockSize();
|
virtual int deviceBlockSize();
|
||||||
};
|
};
|
||||||
|
|
||||||
|
MemoryPort memPort;
|
||||||
|
|
||||||
virtual Port * getPort(const char *if_name);
|
virtual Port * getPort(const char *if_name);
|
||||||
|
|
||||||
int numPorts;
|
int numPorts;
|
||||||
|
@ -101,11 +103,13 @@ class PhysicalMemory : public MemObject
|
||||||
uint64_t size() { return pmem_size; }
|
uint64_t size() { return pmem_size; }
|
||||||
|
|
||||||
public:
|
public:
|
||||||
PhysicalMemory(const std::string &n);
|
PhysicalMemory(const std::string &n, MemObject *bus);
|
||||||
virtual ~PhysicalMemory();
|
virtual ~PhysicalMemory();
|
||||||
|
|
||||||
public:
|
public:
|
||||||
int deviceBlockSize();
|
int deviceBlockSize();
|
||||||
|
void getAddressRanges(AddrRangeList &rangeList, bool &owner);
|
||||||
|
void virtual init() { memPort.sendStatusChange(Port::RangeChange); }
|
||||||
|
|
||||||
// fast back-door memory access for vtophys(), remote gdb, etc.
|
// fast back-door memory access for vtophys(), remote gdb, etc.
|
||||||
// uint64_t phys_read_qword(Addr addr) const;
|
// uint64_t phys_read_qword(Addr addr) const;
|
||||||
|
@ -119,6 +123,7 @@ class PhysicalMemory : public MemObject
|
||||||
public:
|
public:
|
||||||
virtual void serialize(std::ostream &os);
|
virtual void serialize(std::ostream &os);
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/*uint64_t
|
/*uint64_t
|
||||||
|
|
|
@ -73,11 +73,7 @@ class Request
|
||||||
int size;
|
int size;
|
||||||
|
|
||||||
/** The time this request was started. Used to calculate latencies. */
|
/** The time this request was started. Used to calculate latencies. */
|
||||||
Tick requestTime;
|
Tick time;
|
||||||
|
|
||||||
/** The time this request was responded to in the memory hierachy. Used by
|
|
||||||
* deviced to inform ports how long a request should be delayed. */
|
|
||||||
Tick responseTime;
|
|
||||||
|
|
||||||
/** Destination address if this is a block copy. */
|
/** Destination address if this is a block copy. */
|
||||||
Addr copyDest;
|
Addr copyDest;
|
||||||
|
|
|
@ -9,7 +9,7 @@ class BaseCPU(SimObject):
|
||||||
system = Param.System(Parent.any, "system object")
|
system = Param.System(Parent.any, "system object")
|
||||||
cpu_id = Param.Int(-1, "CPU identifier")
|
cpu_id = Param.Int(-1, "CPU identifier")
|
||||||
else:
|
else:
|
||||||
mem = Param.Memory(Parent.any, "memory")
|
mem = Param.MemObject("memory")
|
||||||
workload = VectorParam.Process("processes to run")
|
workload = VectorParam.Process("processes to run")
|
||||||
|
|
||||||
max_insts_all_threads = Param.Counter(0,
|
max_insts_all_threads = Param.Counter(0,
|
||||||
|
|
|
@ -1,7 +1,6 @@
|
||||||
from m5 import *
|
from m5 import *
|
||||||
from BaseHier import BaseHier
|
from MemObject import MemObject
|
||||||
|
|
||||||
class Bus(BaseHier):
|
class Bus(MemObject):
|
||||||
type = 'Bus'
|
type = 'Bus'
|
||||||
clock = Param.Clock("bus frequency")
|
bus_id = Param.Int(0, "blah")
|
||||||
width = Param.Int("bus width in bytes")
|
|
||||||
|
|
|
@ -5,5 +5,6 @@ class PhysicalMemory(Memory):
|
||||||
type = 'PhysicalMemory'
|
type = 'PhysicalMemory'
|
||||||
range = Param.AddrRange("Device Address")
|
range = Param.AddrRange("Device Address")
|
||||||
file = Param.String('', "memory mapped file")
|
file = Param.String('', "memory mapped file")
|
||||||
|
bus = Param.MemObject("Bus to attach to")
|
||||||
if build_env['FULL_SYSTEM']:
|
if build_env['FULL_SYSTEM']:
|
||||||
mmu = Param.MemoryController(Parent.any, "Memory Controller")
|
mmu = Param.MemoryController(Parent.any, "Memory Controller")
|
||||||
|
|
Loading…
Reference in a new issue