diff --git a/dev/io_device.cc b/dev/io_device.cc index 268484e57..5f5f9a09d 100644 --- a/dev/io_device.cc +++ b/dev/io_device.cc @@ -30,8 +30,8 @@ #include "sim/builder.hh" -PioPort::PioPort(PioDevice *dev) - : device(dev) +PioPort::PioPort(PioDevice *dev, Platform *p) + : device(dev), platform(p) { } @@ -75,7 +75,7 @@ PioPort::SendEvent::process() PioDevice::PioDevice(const std::string &name, Platform *p) : SimObject(name), platform(p) { - pioPort = new PioPort(this); + pioPort = new PioPort(this, p); } @@ -83,7 +83,7 @@ bool PioPort::recvTiming(Packet &pkt) { device->recvAtomic(pkt); - sendTiming(pkt, pkt.req->responseTime-pkt.req->requestTime); + sendTiming(pkt, pkt.time-pkt.req->time); return Success; } @@ -148,7 +148,7 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size, basePkt.result = Unknown; basePkt.req = NULL; baseReq.nicReq = true; - baseReq.requestTime = curTick; + baseReq.time = curTick; completionEvent = event; @@ -183,7 +183,7 @@ DmaPort::sendDma(Packet &pkt) transmitList.push_back(&packet); } else if (state == Atomic) {*/ sendAtomic(pkt); - completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime); + completionEvent->schedule(pkt.time - pkt.req->time); completionEvent = NULL; /* } else if (state == Functional) { sendFunctional(pkt); diff --git a/dev/io_device.hh b/dev/io_device.hh index 8e44a1c00..b25048e3d 100644 --- a/dev/io_device.hh +++ b/dev/io_device.hh @@ -57,7 +57,7 @@ class PioPort : public Port /** The platform that device/port are in. This is used to select which mode * we are currently operating in. */ - Platfrom *platform; + Platform *platform; /** A list of outgoing timing response packets that haven't been serviced * yet. */ diff --git a/mem/bus.cc b/mem/bus.cc new file mode 100644 index 000000000..dd72ad3b9 --- /dev/null +++ b/mem/bus.cc @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file Definition of a bus object. + */ + + +#include "bus.hh" +#include "sim/builder.hh" + +/** Function called by the port when the bus is recieving a Timing + * transaction.*/ +bool +Bus::recvTiming(Packet &pkt, int id) +{ + + panic("I need to be implemented, but not right now."); +} + +Port * +Bus::findPort(Addr addr, int id) +{ + /* An interval tree would be a better way to do this. --ali. */ + int dest_id = -1; + int i = 0; + bool found = false; + + while (i < portList.size() && !found) + { + if (portList[i].range == addr) { + dest_id = portList[i].portId; + found = true; + } + } + assert(dest_id != -1 && "Unable to find destination"); + // we shouldn't be sending this back to where it came from + assert(dest_id != id); + + return interfaces[dest_id]; +} + +/** Function called by the port when the bus is recieving a Atomic + * transaction.*/ +Tick +Bus::recvAtomic(Packet &pkt, int id) +{ + return findPort(pkt.addr, id)->sendAtomic(pkt); +} + +/** Function called by the port when the bus is recieving a Functional + * transaction.*/ +void +Bus::recvFunctional(Packet &pkt, int id) +{ + findPort(pkt.addr, id)->sendFunctional(pkt); +} + +/** Function called by the port when the bus is recieving a status change.*/ +void +Bus::recvStatusChange(Port::Status status, int id) +{ + assert(status == Port:: RangeChange && + "The other statuses need to be implemented."); + Port *port = interfaces[id]; + AddrRangeList ranges; + bool owner; + + port->getPeerAddressRanges(ranges, owner); + // not dealing with snooping yet either + assert(owner == true); + // or multiple ranges + assert(ranges.size() == 1); + DevMap dm; + dm.portId = id; + dm.range = ranges.front(); + + portList.push_back(dm); +} + +void +Bus::BusPort::addressRanges(AddrRangeList &range_list, bool &owner) +{ + panic("I'm not implemented.\n"); +} + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus) + + Param bus_id; + +END_DECLARE_SIM_OBJECT_PARAMS(Bus) + +BEGIN_INIT_SIM_OBJECT_PARAMS(Bus) + INIT_PARAM(bus_id, "junk bus id") +END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) + +CREATE_SIM_OBJECT(Bus) +{ + return new Bus(getInstanceName()); +} + +REGISTER_SIM_OBJECT("Bus", Bus) diff --git a/mem/bus.hh b/mem/bus.hh index e26065295..7790bdce3 100644 --- a/mem/bus.hh +++ b/mem/bus.hh @@ -45,6 +45,13 @@ class Bus : public MemObject { + struct DevMap { + int portId; + Range range; + }; + std::vector portList; + + /** Function called by the port when the bus is recieving a Timing transaction.*/ bool recvTiming(Packet &pkt, int id); @@ -60,6 +67,16 @@ class Bus : public MemObject /** Function called by the port when the bus is recieving a status change.*/ void recvStatusChange(Port::Status status, int id); + /** Find which port connected to this bus (if any) should be given a packet + * with this address. + * @param addr Address to find port for. + * @param id Id of the port this packet was received from (to prevent + * loops) + * @return pointer to port that the packet should be sent out of. + */ + Port * + Bus::findPort(Addr addr, int id); + /** Decleration of the buses port type, one will be instantiated for each of the interfaces connecting to the bus. */ class BusPort : public Port @@ -104,6 +121,10 @@ class Bus : public MemObject // the 'owned' address ranges of all the other interfaces on // this bus... virtual void addressRanges(AddrRangeList &range_list, bool &owner); + + // Hack to make translating port work without changes + virtual int deviceBlockSize() { return 32; } + }; /** A count of the number of interfaces connected to this bus. */ @@ -123,6 +144,9 @@ class Bus : public MemObject interfaces[id] = new BusPort(this, id); return interfaces[id]; } + Bus(const std::string &n) + : MemObject(n) {} + }; #endif //__MEM_BUS_HH__ diff --git a/mem/packet.hh b/mem/packet.hh index 57702dc97..ef28a7c9e 100644 --- a/mem/packet.hh +++ b/mem/packet.hh @@ -112,6 +112,9 @@ struct Packet /** The command of the transaction. */ Command cmd; + /** The time this request was responded to. Used to calculate latencies. */ + Tick time; + /** The result of the packet transaction. */ PacketResult result; diff --git a/mem/physical.cc b/mem/physical.cc index c1e83fb9e..e6d1f1662 100644 --- a/mem/physical.cc +++ b/mem/physical.cc @@ -69,8 +69,8 @@ PhysicalMemory::MemResponseEvent::description() return "Physical Memory Timing Access respnse event"; } -PhysicalMemory::PhysicalMemory(const string &n) - : MemObject(n), base_addr(0), pmem_addr(NULL) +PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus) + : MemObject(n), memPort(this), base_addr(0), pmem_addr(NULL) { // Hardcoded to 128 MB for now. pmem_size = 1 << 27; @@ -88,6 +88,14 @@ PhysicalMemory::PhysicalMemory(const string &n) } page_ptr = 0; + + Port *peer_port; + peer_port = bus->getPort(); + memPort.setPeer(peer_port); + peer_port->setPeer(&memPort); + + + } PhysicalMemory::~PhysicalMemory() @@ -181,7 +189,15 @@ void PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list, bool &owner) { - panic("??"); + memory->getAddressRanges(range_list, owner); +} + +void +PhysicalMemory::getAddressRanges(AddrRangeList &range_list, bool &owner) +{ + owner = true; + range_list.clear(); + range_list.push_back(RangeSize(base_addr, pmem_size)); } int @@ -325,6 +341,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) SimObjectParam mmu; #endif Param > range; + SimObjectParam bus; END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) @@ -334,7 +351,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) #if FULL_SYSTEM INIT_PARAM(mmu, "Memory Controller"), #endif - INIT_PARAM(range, "Device Address Range") + INIT_PARAM(range, "Device Address Range"), + INIT_PARAM(bus, "bus object memory connects to") END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) @@ -346,7 +364,7 @@ CREATE_SIM_OBJECT(PhysicalMemory) } #endif - return new PhysicalMemory(getInstanceName()); + return new PhysicalMemory(getInstanceName(), bus); } REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory) diff --git a/mem/physical.hh b/mem/physical.hh index b066d3dfc..2087bf763 100644 --- a/mem/physical.hh +++ b/mem/physical.hh @@ -69,6 +69,8 @@ class PhysicalMemory : public MemObject virtual int deviceBlockSize(); }; + MemoryPort memPort; + virtual Port * getPort(const char *if_name); int numPorts; @@ -101,11 +103,13 @@ class PhysicalMemory : public MemObject uint64_t size() { return pmem_size; } public: - PhysicalMemory(const std::string &n); + PhysicalMemory(const std::string &n, MemObject *bus); virtual ~PhysicalMemory(); public: int deviceBlockSize(); + void getAddressRanges(AddrRangeList &rangeList, bool &owner); + void virtual init() { memPort.sendStatusChange(Port::RangeChange); } // fast back-door memory access for vtophys(), remote gdb, etc. // uint64_t phys_read_qword(Addr addr) const; @@ -119,6 +123,7 @@ class PhysicalMemory : public MemObject public: virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); + }; /*uint64_t diff --git a/mem/request.hh b/mem/request.hh index 1c65057a0..5e2275741 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -73,11 +73,7 @@ class Request int size; /** The time this request was started. Used to calculate latencies. */ - Tick requestTime; - - /** The time this request was responded to in the memory hierachy. Used by - * deviced to inform ports how long a request should be delayed. */ - Tick responseTime; + Tick time; /** Destination address if this is a block copy. */ Addr copyDest; diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index 07cb850f1..fccddb1ec 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -9,7 +9,7 @@ class BaseCPU(SimObject): system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") else: - mem = Param.Memory(Parent.any, "memory") + mem = Param.MemObject("memory") workload = VectorParam.Process("processes to run") max_insts_all_threads = Param.Counter(0, diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py index 26509d7d2..8c5397281 100644 --- a/python/m5/objects/Bus.py +++ b/python/m5/objects/Bus.py @@ -1,7 +1,6 @@ from m5 import * -from BaseHier import BaseHier +from MemObject import MemObject -class Bus(BaseHier): +class Bus(MemObject): type = 'Bus' - clock = Param.Clock("bus frequency") - width = Param.Int("bus width in bytes") + bus_id = Param.Int(0, "blah") diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py index b0aba1a7d..7c5a0c517 100644 --- a/python/m5/objects/PhysicalMemory.py +++ b/python/m5/objects/PhysicalMemory.py @@ -5,5 +5,6 @@ class PhysicalMemory(Memory): type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") + bus = Param.MemObject("Bus to attach to") if build_env['FULL_SYSTEM']: mmu = Param.MemoryController(Parent.any, "Memory Controller")