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stats: Update the stats to reflect the 1GHz default system clock

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This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
This commit is contained in:
Andreas Hansson 2012-10-25 13:15:59 -04:00
parent 6f6adbf0f6
commit b387d8e213
11 changed files with 7769 additions and 7755 deletions
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3236
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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170
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 1.854370 # Nu
sim_ticks 1854370484500 # Number of ticks simulated sim_ticks 1854370484500 # Number of ticks simulated
final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94446 # Simulator instruction rate (inst/s) host_inst_rate 120780 # Simulator instruction rate (inst/s)
host_op_rate 94446 # Simulator op (including micro ops) rate (op/s) host_op_rate 120780 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3304859837 # Simulator tick rate (ticks/s) host_tick_rate 4226353954 # Simulator tick rate (ticks/s)
host_mem_usage 326668 # Number of bytes of host memory used host_mem_usage 326684 # Number of bytes of host memory used
host_seconds 561.10 # Real time elapsed on the host host_seconds 438.76 # Real time elapsed on the host
sim_insts 52993965 # Number of instructions simulated sim_insts 52993965 # Number of instructions simulated
sim_ops 52993965 # Number of ops (including micro ops) simulated sim_ops 52993965 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory
@ -175,14 +175,14 @@ system.physmem.wrQLenPdf::29 7 # Wh
system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests
system.physmem.totBusLat 1780884000 # Total cycles spent in databus access system.physmem.totBusLat 1780884000 # Total cycles spent in databus access
system.physmem.totBankLat 5429382000 # Total cycles spent in bank access system.physmem.totBankLat 5429382000 # Total cycles spent in bank access
system.physmem.avgQLat 13870.66 # Average queueing delay per request system.physmem.avgQLat 13870.65 # Average queueing delay per request
system.physmem.avgBankLat 12194.80 # Average bank access latency per request system.physmem.avgBankLat 12194.80 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30065.46 # Average memory access latency system.physmem.avgMemAccLat 30065.45 # Average memory access latency
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
@ -349,18 +349,18 @@ system.cpu.fetch.Branches 14034298 # Nu
system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total)
@ -372,11 +372,11 @@ system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing
@ -387,7 +387,7 @@ system.cpu.decode.SquashedInsts 129922 # Nu
system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename
@ -414,11 +414,11 @@ system.cpu.iq.iqSquashedInstsIssued 119190 # Nu
system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle
@ -430,7 +430,7 @@ system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available
@ -503,7 +503,7 @@ system.cpu.iq.FU_type_0::total 57151750 # Ty
system.cpu.iq.rate 0.522738 # Inst issue rate system.cpu.iq.rate 0.522738 # Inst issue rate
system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads
@ -556,11 +556,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr
system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle
@ -572,7 +572,7 @@ system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56184240 # Number of instructions committed system.cpu.commit.committedInsts 56184240 # Number of instructions committed
system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -585,10 +585,10 @@ system.cpu.commit.int_insts 52030338 # Nu
system.cpu.commit.function_calls 740415 # Number of function calls committed. system.cpu.commit.function_calls 740415 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 142220967 # The number of ROB reads system.cpu.rob.rob_reads 142220969 # The number of ROB reads
system.cpu.rob.rob_writes 129940455 # The number of ROB writes system.cpu.rob.rob_writes 129940455 # The number of ROB writes
system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52993965 # Number of Instructions Simulated system.cpu.committedInsts 52993965 # Number of Instructions Simulated
system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated
@ -753,16 +753,16 @@ system.cpu.dcache.overall_misses::cpu.data 3743164 #
system.cpu.dcache.overall_misses::total 3743164 # number of overall misses system.cpu.dcache.overall_misses::total 3743164 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445086639 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445061639 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 70445086639 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 70445061639 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 104297759139 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 104297734139 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 104297759139 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 104297734139 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 104297759139 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 104297734139 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 104297759139 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 104297734139 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses)
@ -789,21 +789,21 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.246054
system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 27863.522448 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 27863.522448 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 2571680 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946927 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
@ -833,22 +833,22 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1384956
system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712390769 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712386769 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712386769 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907863269 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907859269 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 31907863269 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 31907859269 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907863269 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907859269 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 31907859269 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997720998 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997718998 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997720998 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421626998 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421628998 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421628998 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses
@ -863,16 +863,16 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039
system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -886,7 +886,7 @@ system.cpu.l2cache.total_refs 2558215 # To
system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 53963.120653 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 53963.120652 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy
@ -930,14 +930,14 @@ system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500
system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496192000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496188000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8496192000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8496188000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20300283500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21216500500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20300283500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21216500500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses)
@ -975,14 +975,14 @@ system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554
system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.450111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.415427 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.450111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52473.228551 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52473.228551 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1021,20 +1021,20 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses
@ -1057,14 +1057,14 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

1590
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
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3050
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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1564
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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1940
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
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1572
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
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22
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 1.910582 # Nu
sim_ticks 1910582068000 # Number of ticks simulated sim_ticks 1910582068000 # Number of ticks simulated
final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1092208 # Simulator instruction rate (inst/s) host_inst_rate 942466 # Simulator instruction rate (inst/s)
host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s) host_op_rate 942466 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37180157619 # Simulator tick rate (ticks/s) host_tick_rate 32082735017 # Simulator tick rate (ticks/s)
host_mem_usage 321564 # Number of bytes of host memory used host_mem_usage 321492 # Number of bytes of host memory used
host_seconds 51.39 # Real time elapsed on the host host_seconds 59.55 # Real time elapsed on the host
sim_insts 56125446 # Number of instructions simulated sim_insts 56125446 # Number of instructions simulated
sim_ops 56125446 # Number of ops (including micro ops) simulated sim_ops 56125446 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@ -815,12 +815,12 @@ system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses

1604
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
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tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 2.603636 # Nu
sim_ticks 2603636076000 # Number of ticks simulated sim_ticks 2603636076000 # Number of ticks simulated
final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 485506 # Simulator instruction rate (inst/s) host_inst_rate 264193 # Simulator instruction rate (inst/s)
host_op_rate 617798 # Simulator op (including micro ops) rate (op/s) host_op_rate 336182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20998999798 # Simulator tick rate (ticks/s) host_tick_rate 11426847777 # Simulator tick rate (ticks/s)
host_mem_usage 395692 # Number of bytes of host memory used host_mem_usage 395692 # Number of bytes of host memory used
host_seconds 123.99 # Real time elapsed on the host host_seconds 227.85 # Real time elapsed on the host
sim_insts 60197128 # Number of instructions simulated sim_insts 60197128 # Number of instructions simulated
sim_ops 76599899 # Number of ops (including micro ops) simulated sim_ops 76599899 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
@ -186,14 +186,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests
system.physmem.totBusLat 61975012000 # Total cycles spent in databus access system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
system.physmem.totBankLat 216184276000 # Total cycles spent in bank access system.physmem.totBankLat 216185438000 # Total cycles spent in bank access
system.physmem.avgQLat 242.42 # Average queueing delay per request system.physmem.avgQLat 242.04 # Average queueing delay per request
system.physmem.avgBankLat 13953.00 # Average bank access latency per request system.physmem.avgBankLat 13953.07 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 18195.41 # Average memory access latency system.physmem.avgMemAccLat 18195.12 # Average memory access latency
system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
@ -202,7 +202,7 @@ system.physmem.peakBW 16000.00 # Th
system.physmem.busUtil 2.51 # Data bus utilization in percentage system.physmem.busUtil 2.51 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.11 # Average read queue length over time system.physmem.avgRdQLen 0.11 # Average read queue length over time
system.physmem.avgWrQLen 12.38 # Average write queue length over time system.physmem.avgWrQLen 12.38 # Average write queue length over time
system.physmem.readRowHits 15449465 # Number of row buffer hits during reads system.physmem.readRowHits 15449450 # Number of row buffer hits during reads
system.physmem.writeRowHits 784611 # Number of row buffer hits during writes system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
@ -285,39 +285,39 @@ system.cpu.num_fp_register_writes 2780 # nu
system.cpu.num_mem_refs 27393681 # number of memory refs system.cpu.num_mem_refs 27393681 # number of memory refs
system.cpu.num_load_insts 15659530 # Number of load instructions system.cpu.num_load_insts 15659530 # Number of load instructions
system.cpu.num_store_insts 11734151 # Number of store instructions system.cpu.num_store_insts 11734151 # Number of store instructions
system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles
system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles
system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.879363 # Percentage of idle cycles system.cpu.idle_fraction 0.879363 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
system.cpu.icache.replacements 855498 # number of replacements system.cpu.icache.replacements 855500 # number of replacements
system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use
system.cpu.icache.total_refs 60635058 # Total number of references to valid blocks. system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 856010 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.834521 # Average number of references to valid blocks. system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 60635058 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60635058 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60635058 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60635058 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60635058 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits
system.cpu.icache.overall_hits::total 60635058 # number of overall hits system.cpu.icache.overall_hits::total 60635056 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856010 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856010 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856010 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856010 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856010 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses
system.cpu.icache.overall_misses::total 856010 # number of overall misses system.cpu.icache.overall_misses::total 856012 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11542526000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11542526000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11542526000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11542526000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11542526000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11542526000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses
@ -330,12 +330,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013921
system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13484.101821 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13484.101821 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13484.101821 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13484.101821 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -344,18 +344,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856010 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 856010 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 856010 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 856010 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856010 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856010 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9830506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9830506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9830506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9830506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9830506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9830506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles
@ -366,12 +366,12 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921
system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11484.101821 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11484.101821 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
@ -408,16 +408,16 @@ system.cpu.dcache.demand_misses::cpu.data 619265 # n
system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses
system.cpu.dcache.overall_misses::total 619265 # number of overall misses system.cpu.dcache.overall_misses::total 619265 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5206335000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205933000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5206335000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5205933000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061427000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061519000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8061427000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8061519000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154571000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154593000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 154571000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 154593000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13267762000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13267452000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13267762000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13267452000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13267762000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13267452000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13267762000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13267452000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses)
@ -440,16 +440,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026033
system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14118.376844 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14117.286713 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14118.376844 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14117.286713 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.088375 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.455637 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.088375 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.455637 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13558.859649 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.789474 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13558.859649 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.789474 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21425.015139 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 21424.514545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21425.015139 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 21424.514545 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -470,22 +470,22 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 619265
system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468809000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468407000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468809000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468407000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560423000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560515000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560423000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560515000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131771000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131793000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131771000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131793000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12029232000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028922000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12029232000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12028922000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12029232000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028922000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12029232000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12028922000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182087740500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182088074500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182087740500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182088074500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708092000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708050000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708092000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708050000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200795832500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200796124500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 200795832500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 200796124500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033
system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12118.376844 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12117.286713 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12118.376844 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12117.286713 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.088375 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.455637 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.088375 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.455637 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11558.859649 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11560.789474 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11558.859649 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11560.789474 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -514,16 +514,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 61906 # number of replacements system.cpu.l2cache.replacements 61906 # number of replacements
system.cpu.l2cache.tagsinuse 50893.840844 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 50893.840705 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1682731 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1682733 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.219871 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 13.219887 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 37868.665500 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 37868.665520 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 6995.476724 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 6995.476581 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6025.811636 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 6025.811619 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
@ -532,9 +532,9 @@ system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Av
system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 843786 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 843788 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226341 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1226343 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
@ -543,14 +543,14 @@ system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 #
system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 843786 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 843788 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1340759 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1340761 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 843786 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 843788 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits
system.cpu.l2cache.overall_hits::total 1340759 # number of overall hits system.cpu.l2cache.overall_hits::total 1340761 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
@ -572,28 +572,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143044 #
system.cpu.l2cache.overall_misses::total 153651 # number of overall misses system.cpu.l2cache.overall_misses::total 153651 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 535011000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 536335000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 517367000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 516987000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1052802500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1053746500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102272500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102367500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6102272500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6102367500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 535011000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 536335000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6619639500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6619354500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 7155075000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 7156114000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 535011000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6619639500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 7155075000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854385 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 854387 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1246806 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1246808 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses)
@ -602,14 +602,14 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604
system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 854385 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 854387 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494410 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 1494412 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 854385 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 854387 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494410 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1494412 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses
@ -631,23 +631,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862
system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50477.497877 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50602.415322 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52481.943599 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52443.396226 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51444.050818 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 51490.178353 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45817.672278 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45818.385566 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45817.672278 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45818.385566 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46567.057813 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 46573.819891 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46567.057813 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 46573.819891 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -679,31 +679,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143044
system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 397346579 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398671075 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389320096 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 388940100 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 786988691 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 787933191 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28812314 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28807316 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28812314 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28807316 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371883715 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371975723 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371883715 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371975723 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 397346579 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398671075 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4761203811 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4760915823 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5158872406 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 5159908914 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 397346579 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398671075 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4761203811 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4760915823 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5158872406 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 5159908914 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688827565 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166886294116 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9174375606 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9174375606 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175863203171 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176060669722 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses
@ -725,23 +725,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency

382
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 5.191113 # Nu
sim_ticks 5191112864000 # Number of ticks simulated sim_ticks 5191112864000 # Number of ticks simulated
final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 414932 # Simulator instruction rate (inst/s) host_inst_rate 1106680 # Simulator instruction rate (inst/s)
host_op_rate 799857 # Simulator op (including micro ops) rate (op/s) host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16795720800 # Simulator tick rate (ticks/s) host_tick_rate 44796411922 # Simulator tick rate (ticks/s)
host_mem_usage 384032 # Number of bytes of host memory used host_mem_usage 384016 # Number of bytes of host memory used
host_seconds 309.07 # Real time elapsed on the host host_seconds 115.88 # Real time elapsed on the host
sim_insts 128244614 # Number of instructions simulated sim_insts 128244614 # Number of instructions simulated
sim_ops 247214605 # Number of ops (including micro ops) simulated sim_ops 247214600 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory
@ -179,14 +179,14 @@ system.physmem.wrQLenPdf::29 1 # Wh
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 2876260269 # Total cycles spent in queuing delays system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 6438486269 # Sum of mem lat for all requests system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests
system.physmem.totBusLat 793712000 # Total cycles spent in databus access system.physmem.totBusLat 793712000 # Total cycles spent in databus access
system.physmem.totBankLat 2768514000 # Total cycles spent in bank access system.physmem.totBankLat 2768514000 # Total cycles spent in bank access
system.physmem.avgQLat 14495.23 # Average queueing delay per request system.physmem.avgQLat 14495.10 # Average queueing delay per request
system.physmem.avgBankLat 13952.23 # Average bank access latency per request system.physmem.avgBankLat 13952.23 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 32447.47 # Average memory access latency system.physmem.avgMemAccLat 32447.33 # Average memory access latency
system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
@ -308,71 +308,71 @@ system.cpu.numCycles 10382225728 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 128244614 # Number of instructions committed system.cpu.committedInsts 128244614 # Number of instructions committed
system.cpu.committedOps 247214605 # Number of ops (including micro ops) committed system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 231949866 # Number of integer alu accesses system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23149724 # number of instructions that are conditional controls system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls
system.cpu.num_int_insts 231949866 # number of integer instructions system.cpu.num_int_insts 231949861 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 566905537 # number of times the integer registers were read system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read
system.cpu.num_int_register_writes 293156479 # number of times the integer registers were written system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 22227093 # number of memory refs system.cpu.num_mem_refs 22227093 # number of memory refs
system.cpu.num_load_insts 13866667 # Number of load instructions system.cpu.num_load_insts 13866667 # Number of load instructions
system.cpu.num_store_insts 8360426 # Number of store instructions system.cpu.num_store_insts 8360426 # Number of store instructions
system.cpu.num_idle_cycles 9781583042.374115 # Number of idle cycles system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles
system.cpu.num_busy_cycles 600642685.625884 # Number of busy cycles system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles
system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942147 # Percentage of idle cycles system.cpu.idle_fraction 0.942147 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.replacements 790930 # number of replacements system.cpu.icache.replacements 790930 # number of replacements
system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use
system.cpu.icache.total_refs 144455336 # Total number of references to valid blocks. system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 182.521696 # Average number of references to valid blocks. system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 144455336 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144455336 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144455336 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144455336 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144455336 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits
system.cpu.icache.overall_hits::total 144455336 # number of overall hits system.cpu.icache.overall_hits::total 144455339 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses
system.cpu.icache.overall_misses::total 791449 # number of overall misses system.cpu.icache.overall_misses::total 791449 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871283000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 10871283000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 10871283000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 10871283000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 10871283000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 10871283000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145246785 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145246785 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145246785 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145246785 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145246785 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145246785 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.923603 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13735.923603 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.923603 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13735.923603 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 13735.921076 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.923603 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13735.923603 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13735.921076 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -387,24 +387,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 791449
system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288385000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288383000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9288385000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 9288383000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288385000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288383000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9288385000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 9288383000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288385000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288383000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9288385000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9288383000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.923603 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.923603 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.923603 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.923603 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.923603 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.923603 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 3663 # number of replacements system.cpu.itb_walker_cache.replacements 3663 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 3.069768 # Cycle average of tags in use system.cpu.itb_walker_cache.tagsinuse 3.069768 # Cycle average of tags in use
@ -570,39 +570,39 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1620900 # number of replacements system.cpu.dcache.replacements 1620901 # number of replacements
system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use
system.cpu.dcache.total_refs 20018689 # Total number of references to valid blocks. system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1621412 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.346454 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 11981581 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11981581 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20016507 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20016507 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20016507 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits
system.cpu.dcache.overall_hits::total 20016507 # number of overall hits system.cpu.dcache.overall_hits::total 20016506 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308144 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308144 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1623630 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1623630 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1623630 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses
system.cpu.dcache.overall_misses::total 1623630 # number of overall misses system.cpu.dcache.overall_misses::total 1623631 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313652000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18313652000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702722500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8702722500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 27016374500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 27016374500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 27016374500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 27016374500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses)
@ -619,14 +619,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.075029
system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.721743 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.721743 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.130560 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.130560 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.489600 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16639.489600 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.489600 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16639.489600 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -635,30 +635,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1538027 # number of writebacks system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks
system.cpu.dcache.writebacks::total 1538027 # number of writebacks system.cpu.dcache.writebacks::total 1538028 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308144 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1308144 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1623630 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1623630 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1623630 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1623630 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697364000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697364000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071750500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071750500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769114500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23769114500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769114500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23769114500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469669500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469669500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616845500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616845500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses
@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029
system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.721743 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.721743 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.130560 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.130560 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.489600 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.489600 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.489600 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.489600 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -683,14 +683,14 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 87015 # number of replacements system.cpu.l2cache.replacements 87015 # number of replacements
system.cpu.l2cache.tagsinuse 64709.520699 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 64709.520704 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3488529 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3488531 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 151765 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 151765 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.986387 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 22.986400 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50328.696687 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 50328.696692 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140121 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140121 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3391.684310 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 3391.684309 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 10988.999582 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 10988.999582 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.767955 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.767955 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
@ -700,10 +700,10 @@ system.cpu.l2cache.occ_percent::total 0.987389 # Av
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6912 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6912 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3076 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3076 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 778529 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 778529 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1278876 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1278877 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2067393 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2067394 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1542258 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 1542259 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1542258 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1542259 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 324 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 324 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 324 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 324 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 199770 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 199770 # number of ReadExReq hits
@ -711,13 +711,13 @@ system.cpu.l2cache.ReadExReq_hits::total 199770 # nu
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6912 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6912 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3076 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3076 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 778529 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 778529 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1478646 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1478647 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2267163 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2267164 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6912 # number of overall hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6912 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3076 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3076 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 778529 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 778529 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1478646 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1478647 # number of overall hits
system.cpu.l2cache.overall_hits::total 2267163 # number of overall hits system.cpu.l2cache.overall_hits::total 2267164 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 12907 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12907 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 28433 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 28433 # number of ReadReq misses
@ -735,28 +735,28 @@ system.cpu.l2cache.overall_misses::cpu.inst 12907 #
system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses
system.cpu.l2cache.overall_misses::total 154875 # number of overall misses system.cpu.l2cache.overall_misses::total 154875 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711633000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599623500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2311601500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723748500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5723748500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 711633000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7323372000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8035350000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 711633000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7323372000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8035350000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307309 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1307310 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2108738 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2108739 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1542258 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1542259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1542258 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1542259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313300 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 313300 # number of ReadExReq accesses(hits+misses)
@ -764,13 +764,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 313300
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6912 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6912 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3081 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3081 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791436 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 791436 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1620609 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1620610 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2422038 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2422039 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6912 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6912 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3081 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3081 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791436 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 791436 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1620609 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1620610 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2422038 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2422039 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001623 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001623 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016308 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021749 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021749 # miss rate for ReadReq accesses
@ -781,28 +781,28 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362368
system.cpu.l2cache.ReadExReq_miss_rate::total 0.362368 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.362368 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001623 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001623 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016308 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016308 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087599 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.087598 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.430387 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56259.399290 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55910.061676 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.176341 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.176341 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.430387 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.483802 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51882.808717 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.430387 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.483802 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51882.808717 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -830,27 +830,27 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907
system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544175395 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1231005255 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775460660 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249338352 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249338352 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544175395 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480343607 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6024799012 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544175395 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480343607 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6024799012 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587770000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587770000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305910000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305910000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893680000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893680000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses
@ -861,28 +861,28 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362368
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362368 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362368 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087599 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.260944 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.947948 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.572500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.211239 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.211239 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.260944 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38604.027859 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.042854 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.260944 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38604.027859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.042854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency