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ruby: rename template_hack to template

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I don't like using the word hack. Hence, the patch.
This commit is contained in:
Nilay Vaish 2012-10-02 14:35:44 -05:00
parent d58f84c481
commit b370f6a7b2
16 changed files with 18 additions and 18 deletions
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2
src/mem/protocol/MESI_CMP_directory-L1cache.sm
View file

@ -126,7 +126,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
bool isPresent(Address);
}
TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
TBETable L1_TBEs, template="<L1Cache_TBE>";
MessageBuffer mandatoryQueue, ordered="false";

2
src/mem/protocol/MESI_CMP_directory-L2cache.sm
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@ -151,7 +151,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
bool isPresent(Address);
}
TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
TBETable L2_TBEs, template="<L2Cache_TBE>";
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();

2
src/mem/protocol/MESI_CMP_directory-dir.sm
View file

@ -105,7 +105,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
// ** OBJECTS **
TBETable TBEs, template_hack="<Directory_TBE>";
TBETable TBEs, template="<Directory_TBE>";
void set_tbe(TBE tbe);
void unset_tbe();

2
src/mem/protocol/MI_example-cache.sm
View file

@ -98,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache")
// STRUCTURES
TBETable TBEs, template_hack="<L1Cache_TBE>";
TBETable TBEs, template="<L1Cache_TBE>";
// PROTOTYPES
void set_cache_entry(AbstractCacheEntry a);

2
src/mem/protocol/MI_example-dir.sm
View file

@ -102,7 +102,7 @@ machine(Directory, "Directory protocol")
}
// ** OBJECTS **
TBETable TBEs, template_hack="<Directory_TBE>";
TBETable TBEs, template="<Directory_TBE>";
void set_tbe(TBE b);
void unset_tbe();

2
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View file

@ -142,7 +142,7 @@ machine(L1Cache, "Directory protocol")
MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
TBETable TBEs, template_hack="<L1Cache_TBE>";
TBETable TBEs, template="<L1Cache_TBE>";
TimerTable useTimerTable;
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";

4
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
View file

@ -225,8 +225,8 @@ machine(L2Cache, "Token protocol")
}
TBETable TBEs, template_hack="<L2Cache_TBE>";
PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>";
TBETable TBEs, template="<L2Cache_TBE>";
PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>";
void set_cache_entry(AbstractCacheEntry b);
void unset_cache_entry();

2
src/mem/protocol/MOESI_CMP_directory-dir.sm
View file

@ -119,7 +119,7 @@ machine(Directory, "Directory protocol")
}
// ** OBJECTS **
TBETable TBEs, template_hack="<Directory_TBE>";
TBETable TBEs, template="<Directory_TBE>";
void set_tbe(TBE b);
void unset_tbe();

2
src/mem/protocol/MOESI_CMP_directory-dma.sm
View file

@ -44,7 +44,7 @@ machine(DMA, "DMA Controller")
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer triggerQueue, ordered="true";
TBETable TBEs, template_hack="<DMA_TBE>";
TBETable TBEs, template="<DMA_TBE>";
State cur_state;
void set_tbe(TBE b);

2
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -180,7 +180,7 @@ machine(L1Cache, "Token protocol")
void wakeUpAllBuffers();
void wakeUpBuffers(Address a);
TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
TBETable L1_TBEs, template="<L1Cache_TBE>";
MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";

2
src/mem/protocol/MOESI_CMP_token-L2cache.sm
View file

@ -146,7 +146,7 @@ machine(L2Cache, "Token protocol")
}
PersistentTable persistentTable;
PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>";
PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>";
void set_cache_entry(AbstractCacheEntry b);
void unset_cache_entry();

2
src/mem/protocol/MOESI_CMP_token-dir.sm
View file

@ -157,7 +157,7 @@ machine(Directory, "Token protocol")
PersistentTable persistentTable;
TimerTable reissueTimerTable;
TBETable TBEs, template_hack="<Directory_TBE>";
TBETable TBEs, template="<Directory_TBE>";
bool starving, default="false";
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";

2
src/mem/protocol/MOESI_hammer-cache.sm
View file

@ -173,7 +173,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
bool isPresent(Address);
}
TBETable TBEs, template_hack="<L1Cache_TBE>";
TBETable TBEs, template="<L1Cache_TBE>";
void set_cache_entry(AbstractCacheEntry b);
void unset_cache_entry();

2
src/mem/protocol/MOESI_hammer-dir.sm
View file

@ -184,7 +184,7 @@ machine(Directory, "AMD Hammer-like protocol")
Set fwd_set;
TBETable TBEs, template_hack="<Directory_TBE>";
TBETable TBEs, template="<Directory_TBE>";
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);

2
src/mem/protocol/Network_test-cache.sm
View file

@ -82,7 +82,7 @@ machine(L1Cache, "Network_test L1 Cache")
// STRUCTURES
TBETable TBEs, template_hack="<L1Cache_TBE>";
TBETable TBEs, template="<L1Cache_TBE>";
// FUNCTIONS

4
src/mem/slicc/symbols/StateMachine.py
View file

@ -385,7 +385,7 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
// Objects
''')
for var in self.objects:
th = var.get("template_hack", "")
th = var.get("template", "")
code('${{var.type.c_ident}}$th* m_${{var.c_ident}}_ptr;')
if var.type.ident == "MessageBuffer":
@ -568,7 +568,7 @@ $c_ident::init()
if "factory" in var:
code('$vid = ${{var["factory"]}};')
elif var.ident.find("mandatoryQueue") < 0:
th = var.get("template_hack", "")
th = var.get("template", "")
expr = "%s = new %s%s" % (vid, vtype.c_ident, th)
args = ""