ARM: Clean up use of TBit and JBit.

Rather tha constantly using ULL(1) << PcXBitShift define those directly.
Additionally, add some helper functions to further clean up the code.

src/arch/arm/faults.cc

@@ -140,7 +140,7 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
     }
 
     Addr pc M5_VAR_USED = tc->readPC();
-    Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
+    Addr newPc = getVector(tc) | (sctlr.te ? PcTBit : 0);
     DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
             name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
     tc->setPC(newPc);

src/arch/arm/insts/static_inst.hh

@@ -43,6 +43,7 @@
 #define __ARCH_ARM_INSTS_STATICINST_HH__
 
 #include "arch/arm/faults.hh"
+#include "arch/arm/utility.hh"
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
 
@@ -219,8 +220,7 @@ class ArmStaticInst : public StaticInst
     readPC(XC *xc)
     {
         Addr pc = xc->readPC();
-        Addr tBit = pc & (ULL(1) << PcTBitShift);
+        if (isThumb(pc))
-        if (tBit)
             return pc + 4;
         else
             return pc + 8;
@@ -232,7 +232,7 @@ class ArmStaticInst : public StaticInst
     setNextPC(XC *xc, Addr val)
     {
         Addr npc = xc->readNextPC();
-        if (npc & (ULL(1) << PcTBitShift)) {
+        if (isThumb(npc)) {
             val &= ~mask(1);
         } else {
             val &= ~mask(2);
@@ -280,8 +280,8 @@ class ArmStaticInst : public StaticInst
     setIWNextPC(XC *xc, Addr val)
     {
         Addr stateBits = xc->readPC() & PcModeMask;
-        Addr jBit = (ULL(1) << PcJBitShift);
+        Addr jBit = PcJBit;
-        Addr tBit = (ULL(1) << PcTBitShift);
+        Addr tBit = PcTBit;
         bool thumbEE = (stateBits == (tBit | jBit));
 
         Addr newPc = (val & ~PcModeMask);
@@ -312,8 +312,8 @@ class ArmStaticInst : public StaticInst
     setAIWNextPC(XC *xc, Addr val)
     {
         Addr stateBits = xc->readPC() & PcModeMask;
-        Addr jBit = (ULL(1) << PcJBitShift);
+        Addr jBit = PcJBit;
-        Addr tBit = (ULL(1) << PcTBitShift);
+        Addr tBit = PcTBit;
         if (!jBit && !tBit) {
             setIWNextPC(xc, val);
         } else {

src/arch/arm/isa.cc

@@ -173,7 +173,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
             cpsr.j = 1;
         else
             cpsr.j = 0;
-        if (pc & (ULL(1) << PcTBitShift))
+        if (isThumb(pc))
             cpsr.t = 1;
         else
             cpsr.t = 0;
@@ -241,9 +241,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
         Addr npc = tc->readNextPC() & ~PcModeMask;
         if (cpsr.j)
-            npc = npc | (ULL(1) << PcJBitShift);
+            npc = npc | PcJBit;
         if (cpsr.t)
-            npc = npc | (ULL(1) << PcTBitShift);
+            npc = npc | PcTBit;
 
         tc->setNextPC(npc);
     } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&

src/arch/arm/isa/insts/branch.isa

@@ -51,8 +51,7 @@ let {{
         '''
         if (link):
             bCode += '''
-                Addr tBit = curPc & (ULL(1) << PcTBitShift);
+                if (!isThumb(curPc))
-                if (!tBit)
                     LR = curPc - 4;
                 else
                     LR = curPc | 1;
@@ -67,10 +66,7 @@ let {{
 
     # BX, BLX
     blxCode = '''
-    Addr curPc = readPC(xc);
+    Addr curPc M5_VAR_USED = readPC(xc);
-    Addr tBit = curPc & (ULL(1) << PcTBitShift);
-    bool arm = !tBit;
-    arm = arm; // In case it's not used otherwise.
     %(link)s
     // Switch modes
     %(branch)s
@@ -86,7 +82,7 @@ let {{
             Name += "Imm"
             # Since we're switching ISAs, the target ISA will be the opposite
             # of the current ISA. !arm is whether the target is ARM.
-            newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
+            newPC = '(isThumb(curPc) ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
             base = "BranchImmCond"
             declare = BranchImmCondDeclare
             constructor = BranchImmCondConstructor
@@ -101,14 +97,14 @@ let {{
                 // The immediate version of the blx thumb instruction
                 // is 32 bits wide, but "next pc" doesn't reflect that
                 // so we don't want to substract 2 from it at this point
-                if (arm)
+                if (!isThumb(curPc))
                     LR = curPc - 4;
                 else
                     LR = curPc  | 1;
             '''
         elif link:
             linkStr = '''
-                if (arm)
+                if (!isThumb(curPc))
                     LR = curPc - 4;
                 else
                     LR = (curPc - 2) | 1;
@@ -119,7 +115,7 @@ let {{
         if imm and link: #blx with imm
             branchStr = '''
                 Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32));
-                FNPC = tempPc ^ (ULL(1) << PcTBitShift);
+                FNPC = tempPc ^ PcTBit;
             '''
         else:
             branchStr = "IWNPC = %(newPC)s;"

src/arch/arm/isa/insts/misc.isa

@@ -638,7 +638,7 @@ let {{
     exec_output += PredOpExecute.subst(mcr15UserIop)
 
     enterxCode = '''
-        FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift);
+        FNPC = NPC | PcJBit | PcTBit;
     '''
     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
                               { "code": enterxCode,
@@ -648,7 +648,7 @@ let {{
     exec_output += PredOpExecute.subst(enterxIop)
 
     leavexCode = '''
-        FNPC = (NPC & ~(1ULL << PcJBitShift)) | (1ULL << PcTBitShift);
+        FNPC = (NPC & ~PcJBit) | PcTBit;
     '''
     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
                               { "code": leavexCode,

src/arch/arm/isa_traits.hh

@@ -127,7 +127,9 @@ namespace ArmISA
     // These otherwise unused bits of the PC are used to select a mode
     // like the J and T bits of the CPSR.
     static const Addr PcJBitShift = 33;
+    static const Addr PcJBit = ULL(1) << PcJBitShift;
     static const Addr PcTBitShift = 34;
+    static const Addr PcTBit = ULL(1) << PcTBitShift;
     static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
                                    (ULL(1) << PcTBitShift);
 };

src/arch/arm/predecoder.cc

@@ -43,6 +43,7 @@
 
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/predecoder.hh"
+#include "arch/arm/utility.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 
@@ -151,7 +152,7 @@ Predecoder::moreBytes(Addr pc, Addr fetchPC, MachInst inst)
 {
     data = inst;
     offset = (fetchPC >= pc) ? 0 : pc - fetchPC;
-    emi.thumb = (pc & (ULL(1) << PcTBitShift)) ? 1 : 0;
+    emi.thumb = isThumb(pc);
     FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
     emi.fpscrLen = fpscr.len;
     emi.fpscrStride = fpscr.stride;

src/arch/arm/process.cc

@@ -362,7 +362,7 @@ ArmLiveProcess::argsInit(int intSize, int pageSize)
 
     Addr prog_entry = objFile->entryPoint();
     if (arch == ObjectFile::Thumb)
-        prog_entry = (prog_entry & ~mask(1)) | (ULL(1) << PcTBitShift);
+        prog_entry = (prog_entry & ~mask(1)) | PcTBit;
     tc->setPC(prog_entry);
     tc->setNextPC(prog_entry + sizeof(MachInst));
 

src/arch/arm/utility.hh

@@ -45,6 +45,7 @@
 #ifndef __ARCH_ARM_UTILITY_HH__
 #define __ARCH_ARM_UTILITY_HH__
 
+#include "arch/arm/isa_traits.hh"
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "base/misc.hh"
@@ -92,6 +93,12 @@ namespace ArmISA {
         tc->activate(0);
     }
 
+    static inline bool
+    isThumb(Addr pc)
+    {
+        return (pc & PcTBit);
+    }
+
     static inline void
     copyRegs(ThreadContext *src, ThreadContext *dest)
     {