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X86: Implement STMXCSR.

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This commit is contained in:
Gabe Black 2009-08-17 20:25:13 -07:00
parent 7fbd9e1296
commit b315c3effc
2 changed files with 11 additions and 2 deletions
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2
src/arch/x86/isa/decoder/two_byte_opcodes.isa
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@ -829,7 +829,7 @@
0x0: fxsave(); 0x0: fxsave();
0x1: fxrstor(); 0x1: fxrstor();
0x2: ldmxcsr(); 0x2: ldmxcsr();
0x3: stmxcsr(); 0x3: Inst::STMXCSR(Md);
0x4: Inst::UD2(); 0x4: Inst::UD2();
0x5: decode MODRM_MOD { 0x5: decode MODRM_MOD {
0x3: BasicOperate::LFENCE( 0x3: BasicOperate::LFENCE(

11
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
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@ -54,6 +54,15 @@
# Authors: Gabe Black # Authors: Gabe Black
microcode = ''' microcode = '''
# STMXCSR def macroop STMXCSR_M {
rdval t1, "InstRegIndex(MISCREG_MXCSR)"
st t1, seg, sib, disp
};
def macroop STMXCSR_P {
rdval t1, "InstRegIndex(MISCREG_MXCSR)"
rdip t7
st t1, seg, riprel, disp
};
# LDMXCSR # LDMXCSR
''' '''