Add support for mmapped iprs to atomic cpu
src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits --HG-- extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
This commit is contained in:
parent
6e9cf9411f
commit
b2eecd643c
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@ -53,6 +53,7 @@ isa_switch_hdrs = Split('''
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isa_traits.hh
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isa_traits.hh
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kernel_stats.hh
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kernel_stats.hh
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locked_mem.hh
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locked_mem.hh
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mmaped_ipr.hh
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process.hh
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process.hh
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regfile.hh
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regfile.hh
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remote_gdb.hh
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remote_gdb.hh
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61
src/arch/alpha/mmaped_ipr.hh
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61
src/arch/alpha/mmaped_ipr.hh
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@ -0,0 +1,61 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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||||||
|
* notice, this list of conditions and the following disclaimer in the
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|
* documentation and/or other materials provided with the distribution;
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|
* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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|
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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||||||
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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||||||
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
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#define __ARCH_ALPHA_MMAPED_IPR_HH__
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/**
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* @file
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*
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* ISA-specific helper functions for memory mapped IPR accesses.
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*/
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#include "mem/packet.hh"
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namespace AlphaISA
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{
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inline Tick
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handleIprRead(ThreadContext *xc, Packet *pkt)
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{
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panic("No handleIprRead implementation in Alpha\n");
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}
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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panic("No handleIprWrite implementation in Alpha\n");
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}
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} // namespace AlphaISA
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#endif
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61
src/arch/mips/mmaped_ipr.hh
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61
src/arch/mips/mmaped_ipr.hh
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@ -0,0 +1,61 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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|
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_MIPS_MMAPED_IPR_HH__
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#define __ARCH_MIPS_MMAPED_IPR_HH__
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/**
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* @file
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*
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* ISA-specific helper functions for memory mapped IPR accesses.
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*/
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#include "mem/packet.hh"
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namespace MipsISA
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{
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inline Tick
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handleIprRead(ThreadContext *xc, Packet *pkt)
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{
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panic("No implementation for handleIprRead in MIPS\n");
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}
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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panic("No implementation for handleIprWrite in MIPS\n");
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}
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} // namespace MipsISA
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#endif
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@ -35,6 +35,7 @@
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namespace SparcISA
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namespace SparcISA
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{
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{
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enum ASI {
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enum ASI {
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ASI_IMPLICIT = 0x00,
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/* Priveleged ASIs */
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/* Priveleged ASIs */
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//0x00-0x03 implementation dependent
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//0x00-0x03 implementation dependent
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ASI_NUCLEUS = 0x4,
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ASI_NUCLEUS = 0x4,
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@ -242,7 +243,6 @@ namespace SparcISA
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ASI_BLK_SL = 0xF9,
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ASI_BLK_SL = 0xF9,
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ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
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ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
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//0xFA-0xFF implementation dependent
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//0xFA-0xFF implementation dependent
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ASI_IMPLICIT = 0xFF,
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MAX_ASI = 0xFF
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MAX_ASI = 0xFF
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};
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};
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@ -32,7 +32,6 @@
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#ifndef __ARCH_SPARC_MISCREGFILE_HH__
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#ifndef __ARCH_SPARC_MISCREGFILE_HH__
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#define __ARCH_SPARC_MISCREGFILE_HH__
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#define __ARCH_SPARC_MISCREGFILE_HH__
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/types.hh"
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#include "arch/sparc/types.hh"
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63
src/arch/sparc/mmaped_ipr.hh
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63
src/arch/sparc/mmaped_ipr.hh
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@ -0,0 +1,63 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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||||||
|
* notice, this list of conditions and the following disclaimer;
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||||||
|
* redistributions in binary form must reproduce the above copyright
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||||||
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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||||||
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* neither the name of the copyright holders nor the names of its
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|
* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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||||||
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||||
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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||||||
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
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#define __ARCH_SPARC_MMAPED_IPR_HH__
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/**
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* @file
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*
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* ISA-specific helper functions for memory mapped IPR accesses.
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*/
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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#include "arch/sparc/tlb.hh"
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namespace SparcISA
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{
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inline Tick
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handleIprRead(ThreadContext *xc, Packet *pkt)
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{
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return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
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}
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
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}
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} // namespace SparcISA
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#endif
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@ -508,13 +508,31 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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req->setPaddr(e->pte.paddr() & ~e->pte.size() |
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req->setPaddr(e->pte.paddr() & ~e->pte.size() |
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req->getVaddr() & e->pte.size());
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req->getVaddr() & e->pte.size());
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return NoFault;
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return NoFault;
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/*** End of normal Path ***/
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/** Normal flow ends here. */
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handleMmuRegAccess:
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handleScratchRegAccess:
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handleScratchRegAccess:
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panic("How are we ever going to deal with this?\n");
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if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
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writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
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return new DataAccessException;
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}
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handleMmuRegAccess:
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req->setMmapedIpr(true);
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req->setPaddr(req->getVaddr());
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return NoFault;
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};
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};
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Tick
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DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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{
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panic("need to implement DTB::doMmuRegRead()\n");
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}
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Tick
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DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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{
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panic("need to implement DTB::doMmuRegWrite()\n");
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}
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void
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void
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TLB::serialize(std::ostream &os)
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TLB::serialize(std::ostream &os)
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{
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{
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@ -38,6 +38,7 @@
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#include "sim/sim_object.hh"
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#include "sim/sim_object.hh"
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class ThreadContext;
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class ThreadContext;
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class Packet;
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namespace SparcISA
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namespace SparcISA
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{
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{
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@ -142,6 +143,8 @@ class DTB : public TLB
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}
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}
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Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
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Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
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Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
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Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
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private:
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private:
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void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
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void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
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@ -29,6 +29,7 @@
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*/
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*/
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#include "arch/locked_mem.hh"
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#include "arch/locked_mem.hh"
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#include "arch/mmaped_ipr.hh"
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#include "arch/utility.hh"
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#include "arch/utility.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/simple/atomic.hh"
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#include "cpu/simple/atomic.hh"
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@ -285,6 +286,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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if (fault == NoFault) {
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if (fault == NoFault) {
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pkt->reinitFromRequest();
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pkt->reinitFromRequest();
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if (req->isMmapedIpr())
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dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
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else
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dcache_latency = dcachePort.sendAtomic(pkt);
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dcache_latency = dcachePort.sendAtomic(pkt);
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dcache_access = true;
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dcache_access = true;
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@ -372,11 +376,15 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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}
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}
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if (do_access) {
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if (do_access) {
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data = htog(data);
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pkt->reinitFromRequest();
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pkt->reinitFromRequest();
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pkt->dataStatic(&data);
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pkt->dataStatic(&data);
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if (req->isMmapedIpr()) {
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dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
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} else {
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data = htog(data);
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dcache_latency = dcachePort.sendAtomic(pkt);
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dcache_latency = dcachePort.sendAtomic(pkt);
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}
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dcache_access = true;
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dcache_access = true;
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assert(pkt->result == Packet::Success);
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assert(pkt->result == Packet::Success);
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@ -49,26 +49,28 @@ class Request;
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typedef Request* RequestPtr;
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typedef Request* RequestPtr;
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/** ASI information for this request if it exsits. */
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const uint32_t ASI_BITS = 0x000FF;
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/** The request is a Load locked/store conditional. */
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/** The request is a Load locked/store conditional. */
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const unsigned LOCKED = 0x001;
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const uint32_t LOCKED = 0x00100;
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/** The virtual address is also the physical address. */
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/** The virtual address is also the physical address. */
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const unsigned PHYSICAL = 0x002;
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const uint32_t PHYSICAL = 0x00200;
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/** The request is an ALPHA VPTE pal access (hw_ld). */
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/** The request is an ALPHA VPTE pal access (hw_ld). */
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const unsigned VPTE = 0x004;
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const uint32_t VPTE = 0x00400;
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/** Use the alternate mode bits in ALPHA. */
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/** Use the alternate mode bits in ALPHA. */
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const unsigned ALTMODE = 0x008;
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const uint32_t ALTMODE = 0x00800;
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/** The request is to an uncacheable address. */
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/** The request is to an uncacheable address. */
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const unsigned UNCACHEABLE = 0x010;
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const uint32_t UNCACHEABLE = 0x01000;
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/** The request should not cause a page fault. */
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/** The request should not cause a page fault. */
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const unsigned NO_FAULT = 0x020;
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const uint32_t NO_FAULT = 0x02000;
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/** The request should be prefetched into the exclusive state. */
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/** The request should be prefetched into the exclusive state. */
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const unsigned PF_EXCLUSIVE = 0x100;
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const uint32_t PF_EXCLUSIVE = 0x10000;
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/** The request should be marked as LRU. */
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/** The request should be marked as LRU. */
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const unsigned EVICT_NEXT = 0x200;
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const uint32_t EVICT_NEXT = 0x20000;
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/** The request should ignore unaligned access faults */
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/** The request should ignore unaligned access faults */
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const unsigned NO_ALIGN_FAULT = 0x400;
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const uint32_t NO_ALIGN_FAULT = 0x40000;
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/** The request was an instruction read. */
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/** The request was an instruction read. */
|
||||||
const unsigned INST_READ = 0x800;
|
const uint32_t INST_READ = 0x80000;
|
||||||
|
|
||||||
class Request
|
class Request
|
||||||
{
|
{
|
||||||
|
@ -95,10 +97,9 @@ class Request
|
||||||
|
|
||||||
/** The address space ID. */
|
/** The address space ID. */
|
||||||
int asid;
|
int asid;
|
||||||
/** The ASI is any -- SPARC ONLY */
|
|
||||||
int asi;
|
|
||||||
/** This request is to a memory mapped register. */
|
/** This request is to a memory mapped register. */
|
||||||
bool mmapedReg;
|
bool mmapedIpr;
|
||||||
|
|
||||||
/** The virtual address of the request. */
|
/** The virtual address of the request. */
|
||||||
Addr vaddr;
|
Addr vaddr;
|
||||||
|
@ -169,6 +170,7 @@ class Request
|
||||||
validAsidVaddr = false;
|
validAsidVaddr = false;
|
||||||
validPC = false;
|
validPC = false;
|
||||||
validScResult = false;
|
validScResult = false;
|
||||||
|
mmapedIpr = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -186,6 +188,7 @@ class Request
|
||||||
validAsidVaddr = true;
|
validAsidVaddr = true;
|
||||||
validPC = true;
|
validPC = true;
|
||||||
validScResult = false;
|
validScResult = false;
|
||||||
|
mmapedIpr = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Set just the physical address. This should only be used to
|
/** Set just the physical address. This should only be used to
|
||||||
|
@ -221,14 +224,17 @@ class Request
|
||||||
int getAsid() { assert(validAsidVaddr); return asid; }
|
int getAsid() { assert(validAsidVaddr); return asid; }
|
||||||
|
|
||||||
/** Accessor function for asi.*/
|
/** Accessor function for asi.*/
|
||||||
int getAsi() { assert(validAsidVaddr); return asi; }
|
uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; }
|
||||||
/** Accessor function for asi.*/
|
|
||||||
void setAsi(int a) { assert(validAsidVaddr); asi = a; }
|
|
||||||
|
|
||||||
/** Accessor function for asi.*/
|
/** Accessor function for asi.*/
|
||||||
bool getMmapedReg() { assert(validPaddr); return mmapedReg; }
|
void setAsi(uint8_t a)
|
||||||
|
{ assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; }
|
||||||
|
|
||||||
/** Accessor function for asi.*/
|
/** Accessor function for asi.*/
|
||||||
void setMmapedReg(bool r) { assert(validPaddr); mmapedReg = r; }
|
bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; }
|
||||||
|
|
||||||
|
/** Accessor function for asi.*/
|
||||||
|
void setMmapedIpr(bool r) { assert(validPaddr); mmapedIpr = r; }
|
||||||
|
|
||||||
/** Accessor function to check if sc result is valid. */
|
/** Accessor function to check if sc result is valid. */
|
||||||
bool scResultValid() { return validScResult; }
|
bool scResultValid() { return validScResult; }
|
||||||
|
|
Loading…
Reference in a new issue