ARM: Turn on the page table walker on ARM in SE mode.
This commit is contained in:
parent
dd8fed7387
commit
b2af015b97
5 changed files with 36 additions and 59 deletions
|
@ -37,15 +37,12 @@
|
||||||
#
|
#
|
||||||
# Authors: Ali Saidi
|
# Authors: Ali Saidi
|
||||||
|
|
||||||
from m5.defines import buildEnv
|
|
||||||
from m5.SimObject import SimObject
|
from m5.SimObject import SimObject
|
||||||
from m5.params import *
|
from m5.params import *
|
||||||
from m5.proxy import *
|
from m5.proxy import *
|
||||||
|
from MemObject import MemObject
|
||||||
|
|
||||||
if buildEnv['FULL_SYSTEM']:
|
class ArmTableWalker(MemObject):
|
||||||
from MemObject import MemObject
|
|
||||||
|
|
||||||
class ArmTableWalker(MemObject):
|
|
||||||
type = 'ArmTableWalker'
|
type = 'ArmTableWalker'
|
||||||
cxx_class = 'ArmISA::TableWalker'
|
cxx_class = 'ArmISA::TableWalker'
|
||||||
port = Port("Port for TableWalker to do walk the translation with")
|
port = Port("Port for TableWalker to do walk the translation with")
|
||||||
|
@ -58,5 +55,4 @@ class ArmTLB(SimObject):
|
||||||
type = 'ArmTLB'
|
type = 'ArmTLB'
|
||||||
cxx_class = 'ArmISA::TLB'
|
cxx_class = 'ArmISA::TLB'
|
||||||
size = Param.Int(64, "TLB size")
|
size = Param.Int(64, "TLB size")
|
||||||
if buildEnv['FULL_SYSTEM']:
|
|
||||||
walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
|
walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
|
||||||
|
|
|
@ -59,6 +59,7 @@ if env['TARGET_ISA'] == 'arm':
|
||||||
Source('miscregs.cc')
|
Source('miscregs.cc')
|
||||||
Source('predecoder.cc')
|
Source('predecoder.cc')
|
||||||
Source('nativetrace.cc')
|
Source('nativetrace.cc')
|
||||||
|
Source('table_walker.cc')
|
||||||
Source('tlb.cc')
|
Source('tlb.cc')
|
||||||
Source('utility.cc')
|
Source('utility.cc')
|
||||||
Source('remote_gdb.cc')
|
Source('remote_gdb.cc')
|
||||||
|
@ -76,7 +77,6 @@ if env['TARGET_ISA'] == 'arm':
|
||||||
Source('system.cc')
|
Source('system.cc')
|
||||||
Source('vtophys.cc')
|
Source('vtophys.cc')
|
||||||
Source('linux/system.cc')
|
Source('linux/system.cc')
|
||||||
Source('table_walker.cc')
|
|
||||||
|
|
||||||
SimObject('ArmSystem.py')
|
SimObject('ArmSystem.py')
|
||||||
else:
|
else:
|
||||||
|
|
|
@ -47,6 +47,7 @@
|
||||||
|
|
||||||
#include "arch/arm/faults.hh"
|
#include "arch/arm/faults.hh"
|
||||||
#include "arch/arm/pagetable.hh"
|
#include "arch/arm/pagetable.hh"
|
||||||
|
#include "arch/arm/table_walker.hh"
|
||||||
#include "arch/arm/tlb.hh"
|
#include "arch/arm/tlb.hh"
|
||||||
#include "arch/arm/utility.hh"
|
#include "arch/arm/utility.hh"
|
||||||
#include "base/inifile.hh"
|
#include "base/inifile.hh"
|
||||||
|
@ -58,29 +59,24 @@
|
||||||
#include "debug/TLBVerbose.hh"
|
#include "debug/TLBVerbose.hh"
|
||||||
#include "mem/page_table.hh"
|
#include "mem/page_table.hh"
|
||||||
#include "params/ArmTLB.hh"
|
#include "params/ArmTLB.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
#include "sim/process.hh"
|
#include "sim/process.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
#include "arch/arm/system.hh"
|
#include "arch/arm/system.hh"
|
||||||
#include "arch/arm/table_walker.hh"
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace ArmISA;
|
using namespace ArmISA;
|
||||||
|
|
||||||
TLB::TLB(const Params *p)
|
TLB::TLB(const Params *p)
|
||||||
: BaseTLB(p), size(p->size)
|
: BaseTLB(p), size(p->size) , tableWalker(p->walker),
|
||||||
#if FULL_SYSTEM
|
rangeMRU(1), bootUncacheability(false), miscRegValid(false)
|
||||||
, tableWalker(p->walker)
|
|
||||||
#endif
|
|
||||||
, rangeMRU(1), bootUncacheability(false), miscRegValid(false)
|
|
||||||
{
|
{
|
||||||
table = new TlbEntry[size];
|
table = new TlbEntry[size];
|
||||||
memset(table, 0, sizeof(TlbEntry) * size);
|
memset(table, 0, sizeof(TlbEntry) * size);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
tableWalker->setTlb(this);
|
tableWalker->setTlb(this);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
TLB::~TLB()
|
TLB::~TLB()
|
||||||
|
@ -404,7 +400,6 @@ TLB::regStats()
|
||||||
accesses = readAccesses + writeAccesses + instAccesses;
|
accesses = readAccesses + writeAccesses + instAccesses;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !FULL_SYSTEM
|
|
||||||
Fault
|
Fault
|
||||||
TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
|
TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
Translation *translation, bool &delay, bool timing)
|
Translation *translation, bool &delay, bool timing)
|
||||||
|
@ -426,18 +421,18 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
Addr paddr;
|
Addr paddr;
|
||||||
Process *p = tc->getProcessPtr();
|
Process *p = tc->getProcessPtr();
|
||||||
|
|
||||||
if (!p->pTable->translate(vaddr, paddr))
|
if (!p->pTable->translate(vaddr, paddr))
|
||||||
return Fault(new GenericPageTableFault(vaddr));
|
return Fault(new GenericPageTableFault(vaddr));
|
||||||
req->setPaddr(paddr);
|
req->setPaddr(paddr);
|
||||||
|
#endif
|
||||||
|
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
#else // FULL_SYSTEM
|
|
||||||
|
|
||||||
Fault
|
Fault
|
||||||
TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
|
TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
|
||||||
{
|
{
|
||||||
|
@ -578,10 +573,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
if (!bootUncacheability &&
|
if (!bootUncacheability &&
|
||||||
((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
|
((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
|
||||||
req->setFlags(Request::UNCACHEABLE);
|
req->setFlags(Request::UNCACHEABLE);
|
||||||
|
#endif
|
||||||
|
|
||||||
switch ( (dacr >> (te->domain * 2)) & 0x3) {
|
switch ( (dacr >> (te->domain * 2)) & 0x3) {
|
||||||
case 0:
|
case 0:
|
||||||
|
@ -684,18 +680,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
Fault
|
Fault
|
||||||
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
||||||
{
|
{
|
||||||
bool delay = false;
|
bool delay = false;
|
||||||
Fault fault;
|
Fault fault;
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
fault = translateFs(req, tc, mode, NULL, delay, false);
|
fault = translateFs(req, tc, mode, NULL, delay, false);
|
||||||
#else
|
else
|
||||||
fault = translateSe(req, tc, mode, NULL, delay, false);
|
fault = translateSe(req, tc, mode, NULL, delay, false);
|
||||||
#endif
|
|
||||||
assert(!delay);
|
assert(!delay);
|
||||||
return fault;
|
return fault;
|
||||||
}
|
}
|
||||||
|
@ -707,11 +700,10 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
||||||
assert(translation);
|
assert(translation);
|
||||||
bool delay = false;
|
bool delay = false;
|
||||||
Fault fault;
|
Fault fault;
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
fault = translateFs(req, tc, mode, translation, delay, true);
|
fault = translateFs(req, tc, mode, translation, delay, true);
|
||||||
#else
|
else
|
||||||
fault = translateSe(req, tc, mode, translation, delay, true);
|
fault = translateSe(req, tc, mode, translation, delay, true);
|
||||||
#endif
|
|
||||||
DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
|
DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
|
||||||
NoFault);
|
NoFault);
|
||||||
if (!delay)
|
if (!delay)
|
||||||
|
@ -724,11 +716,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
||||||
Port*
|
Port*
|
||||||
TLB::getPort()
|
TLB::getPort()
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
|
||||||
return tableWalker->getPort("port");
|
return tableWalker->getPort("port");
|
||||||
#else
|
|
||||||
return NULL;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -89,9 +89,7 @@ class TLB : public BaseTLB
|
||||||
|
|
||||||
uint32_t _attr; // Memory attributes for last accessed TLB entry
|
uint32_t _attr; // Memory attributes for last accessed TLB entry
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
TableWalker *tableWalker;
|
TableWalker *tableWalker;
|
||||||
#endif
|
|
||||||
|
|
||||||
/** Lookup an entry in the TLB
|
/** Lookup an entry in the TLB
|
||||||
* @param vpn virtual address
|
* @param vpn virtual address
|
||||||
|
@ -195,13 +193,10 @@ class TLB : public BaseTLB
|
||||||
return _attr;
|
return _attr;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
|
Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
Translation *translation, bool &delay, bool timing);
|
Translation *translation, bool &delay, bool timing);
|
||||||
#else
|
|
||||||
Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
|
Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
Translation *translation, bool &delay, bool timing);
|
Translation *translation, bool &delay, bool timing);
|
||||||
#endif
|
|
||||||
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
|
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
|
||||||
Fault translateTiming(RequestPtr req, ThreadContext *tc,
|
Fault translateTiming(RequestPtr req, ThreadContext *tc,
|
||||||
Translation *translation, Mode mode);
|
Translation *translation, Mode mode);
|
||||||
|
|
|
@ -140,8 +140,7 @@ class BaseCPU(MemObject):
|
||||||
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
|
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
|
||||||
|
|
||||||
_cached_ports = []
|
_cached_ports = []
|
||||||
if buildEnv['TARGET_ISA'] == 'x86' or \
|
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
|
||||||
(buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']):
|
|
||||||
_cached_ports = ["itb.walker.port", "dtb.walker.port"]
|
_cached_ports = ["itb.walker.port", "dtb.walker.port"]
|
||||||
|
|
||||||
_uncached_ports = []
|
_uncached_ports = []
|
||||||
|
@ -169,8 +168,7 @@ class BaseCPU(MemObject):
|
||||||
self.icache_port = ic.cpu_side
|
self.icache_port = ic.cpu_side
|
||||||
self.dcache_port = dc.cpu_side
|
self.dcache_port = dc.cpu_side
|
||||||
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
|
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
|
||||||
if buildEnv['FULL_SYSTEM']:
|
if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
|
||||||
if buildEnv['TARGET_ISA'] == 'x86':
|
|
||||||
self.itb_walker_cache = iwc
|
self.itb_walker_cache = iwc
|
||||||
self.dtb_walker_cache = dwc
|
self.dtb_walker_cache = dwc
|
||||||
self.itb.walker.port = iwc.cpu_side
|
self.itb.walker.port = iwc.cpu_side
|
||||||
|
|
Loading…
Reference in a new issue