Ports now have a pointer to the MemObject that owns it (can be NULL).

src/cpu/simple/atomic.hh:
    Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
    Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
    Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
    Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
    Ports now optionally take in the MemObject that owns it.

--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
This commit is contained in:
Kevin Lim 2006-10-31 13:59:30 -05:00
parent eda7148af2
commit b26355daa8
7 changed files with 31 additions and 20 deletions

View file

@ -87,7 +87,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public: public:
CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
: Port(_name), cpu(_cpu) : Port(_name, _cpu), cpu(_cpu)
{ } { }
protected: protected:

View file

@ -79,7 +79,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public: public:
CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
: Port(_name), cpu(_cpu), lat(_lat) : Port(_name, _cpu), cpu(_cpu), lat(_lat)
{ } { }
protected: protected:
@ -166,6 +166,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
PacketPtr ifetch_pkt; PacketPtr ifetch_pkt;
PacketPtr dcache_pkt; PacketPtr dcache_pkt;
int cpu_id; int cpu_id;
Tick previousTick; Tick previousTick;

View file

@ -37,7 +37,7 @@
PioPort::PioPort(PioDevice *dev, System *s, std::string pname) PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
: SimpleTimingPort(dev->name() + pname), device(dev) : SimpleTimingPort(dev->name() + pname, dev), device(dev)
{ } { }
@ -92,8 +92,8 @@ BasicPioDevice::addressRanges(AddrRangeList &range_list)
DmaPort::DmaPort(DmaDevice *dev, System *s) DmaPort::DmaPort(DmaDevice *dev, System *s)
: Port(dev->name() + "-dmaport"), device(dev), sys(s), pendingCount(0), : Port(dev->name() + "-dmaport", dev), device(dev), sys(s),
actionInProgress(0), drainEvent(NULL) pendingCount(0), actionInProgress(0), drainEvent(NULL)
{ } { }
bool bool

View file

@ -144,7 +144,7 @@ class Bus : public MemObject
/** Constructor for the BusPort.*/ /** Constructor for the BusPort.*/
BusPort(const std::string &_name, Bus *_bus, int _id) BusPort(const std::string &_name, Bus *_bus, int _id)
: Port(_name), _onRetryList(false), bus(_bus), id(_id) : Port(_name, _bus), _onRetryList(false), bus(_bus), id(_id)
{ } { }
bool onRetryList() bool onRetryList()

View file

@ -42,7 +42,7 @@ using namespace std;
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
bool _isCpuSide) bool _isCpuSide)
: Port(_name), cache(_cache), isCpuSide(_isCpuSide) : Port(_name, _cache), cache(_cache), isCpuSide(_isCpuSide)
{ {
blocked = false; blocked = false;
waitingOnRetry = false; waitingOnRetry = false;

View file

@ -58,6 +58,8 @@
typedef std::list<Range<Addr> > AddrRangeList; typedef std::list<Range<Addr> > AddrRangeList;
typedef std::list<Range<Addr> >::iterator AddrRangeIter; typedef std::list<Range<Addr> >::iterator AddrRangeIter;
class MemObject;
/** /**
* Ports are used to interface memory objects to * Ports are used to interface memory objects to
* each other. They will always come in pairs, and we refer to the other * each other. They will always come in pairs, and we refer to the other
@ -81,10 +83,13 @@ class Port
memory objects. */ memory objects. */
Port *peer; Port *peer;
/** A pointer to the MemObject that owns this port. This may not be set. */
MemObject *owner;
public: public:
Port() Port()
: peer(NULL) : peer(NULL), owner(NULL)
{ } { }
/** /**
@ -92,9 +97,11 @@ class Port
* *
* @param _name Port name for DPRINTF output. Should include name * @param _name Port name for DPRINTF output. Should include name
* of memory system object to which the port belongs. * of memory system object to which the port belongs.
* @param _owner Pointer to the MemObject that owns this port.
* Will not necessarily be set.
*/ */
Port(const std::string &_name) Port(const std::string &_name, MemObject *_owner = NULL)
: portName(_name), peer(NULL) : portName(_name), peer(NULL), owner(_owner)
{ } { }
/** Return port name (for DPRINTF). */ /** Return port name (for DPRINTF). */
@ -112,16 +119,18 @@ class Port
void setName(const std::string &name) void setName(const std::string &name)
{ portName = name; } { portName = name; }
/** Function to set the pointer for the peer port. /** Function to set the pointer for the peer port. */
@todo should be called by the configuration stuff (python).
*/
void setPeer(Port *port); void setPeer(Port *port);
/** Function to set the pointer for the peer port. /** Function to get the pointer to the peer port. */
@todo should be called by the configuration stuff (python).
*/
Port *getPeer() { return peer; } Port *getPeer() { return peer; }
/** Function to set the owner of this port. */
void setOwner(MemObject *_owner) { owner = _owner; }
/** Function to return the owner of this port. */
MemObject *getOwner() { return owner; }
protected: protected:
/** These functions are protected because they should only be /** These functions are protected because they should only be
@ -247,8 +256,8 @@ class Port
class FunctionalPort : public Port class FunctionalPort : public Port
{ {
public: public:
FunctionalPort(const std::string &_name) FunctionalPort(const std::string &_name, MemObject *_owner = NULL)
: Port(_name) : Port(_name, _owner)
{} {}
protected: protected:

View file

@ -117,8 +117,8 @@ class SimpleTimingPort : public Port
public: public:
SimpleTimingPort(std::string pname) SimpleTimingPort(std::string pname, MemObject *_owner = NULL)
: Port(pname), outTiming(0), drainEvent(NULL) : Port(pname, _owner), outTiming(0), drainEvent(NULL)
{} {}
/** Hook for draining timing accesses from the system. The /** Hook for draining timing accesses from the system. The