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X86: Hook in the M5 pseudo insts.

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This commit is contained in:
Gabe Black 2009-01-06 23:55:46 -08:00
parent 115b1a7ed3
commit b23633ad1b
5 changed files with 104 additions and 3 deletions
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92
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -163,8 +163,96 @@
} }
0x02: lar_Gv_Ew(); 0x02: lar_Gv_Ew();
0x03: lsl_Gv_Ew(); 0x03: lsl_Gv_Ew();
//sandpile.org doesn't seem to know what this is... ? // sandpile.org doesn't seem to know what this is...? We'll
0x04: loadall_or_reset_or_hang(); // use it for pseudo instructions. We've got 16 bits of space
// to play with so there can be quite a few pseudo
// instructions.
//0x04: loadall_or_reset_or_hang();
0x4: decode IMMEDIATE {
format BasicOperate {
#if FULL_SYSTEM
0x00: m5arm({{
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: m5quiesce({{
PseudoInst::quiesce(xc->tcBase());
}}, IsNonSpeculative);
0x02: m5quiesceNs({{
PseudoInst::quiesceNs(xc->tcBase(), Rdi);
}}, IsNonSpeculative);
0x03: m5quiesceCycle({{
PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
}}, IsNonSpeculative);
0x04: m5quiesceTime({{
Rax = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative);
#endif
0x07: m5rpns({{
Rax = PseudoInst::rpns(xc->tcBase());
}}, IsNonSpeculative);
0x21: m5exit({{
PseudoInst::m5exit(xc->tcBase(), Rdi);
}}, IsNonSpeculative);
#if FULL_SYSTEM
0x30: m5initparam({{
Rax = xc->tcBase()->getCpuPtr()->
system->init_param;
}}, IsNonSpeculative);
0x31: m5loadsymbol({{
PseudoInst::loadsymbol(xc->tcBase());
}}, IsNonSpeculative);
#endif
0x40: m5resetstats({{
PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
0x41: m5dumpstats({{
PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
0x42: m5dumpresetstats({{
PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
#if FULL_SYSTEM
0x50: m5readfile({{
Rax = PseudoInst::readfile(
xc->tcBase(), Rdi, Rsi, Rdx);
}}, IsNonSpeculative);
#endif
0x51: m5debugbreak({{
PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
#if FULL_SYSTEM
0x53: m5addsymbol({{
PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
#endif
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.\n",
xc->readPC());
}}, IsNonSpeculative);
0x55: m5reserved1({{
warn("M5 reserved opcode 1 ignored.\n");
}}, IsNonSpeculative);
0x56: m5reserved2({{
warn("M5 reserved opcode 2 ignored.\n");
}}, IsNonSpeculative);
0x57: m5reserved3({{
warn("M5 reserved opcode 3 ignored.\n");
}}, IsNonSpeculative);
0x58: m5reserved4({{
warn("M5 reserved opcode 4 ignored.\n");
}}, IsNonSpeculative);
0x59: m5reserved5({{
warn("M5 reserved opcode 5 ignored.\n");
}}, IsNonSpeculative);
default: Inst::UD2();
}
}
#if FULL_SYSTEM #if FULL_SYSTEM
0x05: syscall(); 0x05: syscall();
#else #else

8
src/arch/x86/isa/formats/basic.isa
View file

@ -147,3 +147,11 @@ def template BasicDecode {{
def template BasicDecodeWithMnemonic {{ def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst); return new %(class_name)s("%(mnemonic)s", machInst);
}}; }};
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'X86ISA::X86StaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

1
src/arch/x86/isa/includes.isa
View file

@ -156,6 +156,7 @@ output exec {{
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh" #include "mem/packet_access.hh"
#include "sim/pseudo_inst.hh"
using namespace X86ISA; using namespace X86ISA;
using namespace std; using namespace std;

4
src/arch/x86/isa/operands.isa
View file

@ -113,6 +113,10 @@ def operands {{
'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13), 'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14), 'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15), 'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
'Rsp': ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16),
'Rbp': ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17),
'Rsi': ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18),
'Rdi': ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19),
'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),

2
src/arch/x86/predecoder_tables.cc
View file

@ -201,7 +201,7 @@ namespace X86ISA
//For two byte instructions //For two byte instructions
{ //LSB { //LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F // MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY , /* 0 */ 0 , 0 , 0 , 0 , WO, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY ,
/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , /* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , /* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , /* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,