Record numCycles properly.
src/cpu/simple/timing.cc: Record numCycles stat properly. src/cpu/simple/timing.hh: Extra variable to help record numCycles stat. --HG-- extra : convert_revision : 343311902831820264878aad41dc619999726b6b
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2 changed files with 31 additions and 0 deletions
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@ -100,6 +100,7 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
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ifetch_pkt = dcache_pkt = NULL;
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ifetch_pkt = dcache_pkt = NULL;
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drainEvent = NULL;
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drainEvent = NULL;
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fetchEvent = NULL;
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fetchEvent = NULL;
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previousTick = 0;
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changeState(SimObject::Running);
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changeState(SimObject::Running);
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}
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}
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@ -158,6 +159,7 @@ TimingSimpleCPU::resume()
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assert(system->getMemoryMode() == System::Timing);
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assert(system->getMemoryMode() == System::Timing);
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changeState(SimObject::Running);
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changeState(SimObject::Running);
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previousTick = curTick;
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}
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}
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void
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void
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@ -165,6 +167,7 @@ TimingSimpleCPU::switchOut()
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{
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{
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assert(status() == Running || status() == Idle);
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assert(status() == Running || status() == Idle);
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_status = SwitchedOut;
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_status = SwitchedOut;
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numCycles += curTick - previousTick;
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// If we've been scheduled to resume but are then told to switch out,
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// If we've been scheduled to resume but are then told to switch out,
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// we'll need to cancel it.
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// we'll need to cancel it.
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@ -187,6 +190,23 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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break;
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break;
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}
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}
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}
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}
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Port *peer;
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if (icachePort.getPeer() == NULL) {
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peer = oldCPU->getPort("icachePort")->getPeer();
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icachePort.setPeer(peer);
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} else {
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peer = icachePort.getPeer();
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}
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peer->setPeer(&icachePort);
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if (dcachePort.getPeer() == NULL) {
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peer = oldCPU->getPort("dcachePort")->getPeer();
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dcachePort.setPeer(peer);
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} else {
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peer = dcachePort.getPeer();
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}
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peer->setPeer(&dcachePort);
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}
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}
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@ -414,6 +434,9 @@ TimingSimpleCPU::fetch()
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// fetch fault: advance directly to next instruction (fault handler)
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// fetch fault: advance directly to next instruction (fault handler)
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advanceInst(fault);
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advanceInst(fault);
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}
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}
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numCycles += curTick - previousTick;
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previousTick = curTick;
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}
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}
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@ -444,6 +467,9 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
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delete pkt->req;
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delete pkt->req;
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delete pkt;
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delete pkt;
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numCycles += curTick - previousTick;
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previousTick = curTick;
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if (getState() == SimObject::Draining) {
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if (getState() == SimObject::Draining) {
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completeDrain();
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completeDrain();
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return;
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return;
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@ -516,6 +542,9 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
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assert(_status == DcacheWaitResponse);
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assert(_status == DcacheWaitResponse);
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_status = Running;
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_status = Running;
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numCycles += curTick - previousTick;
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previousTick = curTick;
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if (getState() == SimObject::Draining) {
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if (getState() == SimObject::Draining) {
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completeDrain();
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completeDrain();
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@ -166,6 +166,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
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Packet *ifetch_pkt;
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Packet *ifetch_pkt;
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Packet *dcache_pkt;
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Packet *dcache_pkt;
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Tick previousTick;
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public:
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public:
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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