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Fixes for ll/sc for the O3 model.

Browse source 
cpu/o3/alpha_cpu.hh:
    Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
    Setup request parameters when they're needed.

--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
This commit is contained in:
Kevin Lim 2006-04-24 16:59:50 -04:00
parent b363a3703d
commit b14bf03219
2 changed files with 5 additions and 4 deletions
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3
cpu/o3/alpha_cpu.hh
View file

@ -425,9 +425,10 @@ class AlphaFullCPU : public FullO3CPU<Impl>
req->result = 2;
} else {
if (this->lockFlag/* && this->lockAddr == req->paddr*/) {
req->result=1;
req->result = 1;
} else {
req->result = 0;
return NoFault;
}
}
}

6
cpu/o3/lsq_unit.hh
View file

@ -566,6 +566,9 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
DPRINTF(LSQUnit, "Doing functional access for inst PC %#x\n",
loadQueue[load_idx]->readPC());
assert(!req->data);
req->cmd = Read;
req->completionEvent = NULL;
req->time = curTick;
req->data = new uint8_t[64];
Fault fault = cpu->read(req, data);
memcpy(req->data, &data, sizeof(T));
@ -587,9 +590,6 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
}
DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
loadQueue[load_idx]->readPC());
req->cmd = Read;
req->completionEvent = NULL;
req->time = curTick;
assert(!req->completionEvent);
req->completionEvent =