X86: Change the Opteron platform to be the PC platform.

--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
This commit is contained in:
Gabe Black 2008-03-25 02:06:53 -04:00
parent 623dd7ed3a
commit b0c52885ce
6 changed files with 82 additions and 50 deletions

View file

@ -177,19 +177,12 @@ def makeLinuxX86System(mem_mode, mdesc = None):
self.bridge.side_a = self.iobus.port self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port self.bridge.side_b = self.membus.port
# Serial port and console
self.console = SimConsole()
self.com_1 = Uart8250()
self.com_1.pio_addr = x86IOAddress(0x3f8)
self.com_1.pio = self.iobus.port
self.com_1.sim_console = self.console
# Command line # Command line
self.boot_osflags = 'earlyprintk=ttyS0' self.boot_osflags = 'earlyprintk=ttyS0'
# Platform # Platform
self.opteron = Opteron() self.pc = PC()
self.opteron.attachIO(self.iobus) self.pc.attachIO(self.iobus)
self.intrctrl = IntrControl() self.intrctrl = IntrControl()

View file

@ -1,18 +0,0 @@
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
from Uart import Uart8250
from Platform import Platform
from Pci import PciConfigAll
from SimConsole import SimConsole
class Opteron(Platform):
type = 'Opteron'
system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
def attachIO(self, bus):
self.pciconfig.pio = bus.default
bus.responder_set = True
bus.responder = self.pciconfig

57
src/dev/x86/PC.py Normal file
View file

@ -0,0 +1,57 @@
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
from Uart import Uart8250
from Platform import Platform
from Pci import PciConfigAll
from SimConsole import SimConsole
def x86IOAddress(port):
IO_address_space_base = 0x8000000000000000
return IO_address_space_base + port;
class PC(Platform):
type = 'PC'
system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
# Serial port and console
console = SimConsole()
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
com_1.sim_console = console
def attachIO(self, bus):
self.com_1.pio = bus.port
self.pciconfig.pio = bus.default
bus.responder_set = True
bus.responder = self.pciconfig

View file

@ -32,6 +32,6 @@
Import('*') Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86': if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
SimObject('Opteron.py') SimObject('PC.py')
Source('opteron.cc') Source('pc.cc')

View file

@ -29,7 +29,7 @@
*/ */
/** @file /** @file
* Implementation of Opteron platform. * Implementation of PC platform.
*/ */
#include <deque> #include <deque>
@ -39,13 +39,13 @@
#include "arch/x86/x86_traits.hh" #include "arch/x86/x86_traits.hh"
#include "cpu/intr_control.hh" #include "cpu/intr_control.hh"
#include "dev/simconsole.hh" #include "dev/simconsole.hh"
#include "dev/x86/opteron.hh" #include "dev/x86/pc.hh"
#include "sim/system.hh" #include "sim/system.hh"
using namespace std; using namespace std;
using namespace TheISA; using namespace TheISA;
Opteron::Opteron(const Params *p) PC::PC(const Params *p)
: Platform(p), system(p->system) : Platform(p), system(p->system)
{ {
// set the back pointer from the system to myself // set the back pointer from the system to myself
@ -53,40 +53,40 @@ Opteron::Opteron(const Params *p)
} }
Tick Tick
Opteron::intrFrequency() PC::intrFrequency()
{ {
panic("Need implementation\n"); panic("Need implementation\n");
M5_DUMMY_RETURN M5_DUMMY_RETURN
} }
void void
Opteron::postConsoleInt() PC::postConsoleInt()
{ {
warn_once("Don't know what interrupt to post for console.\n"); warn_once("Don't know what interrupt to post for console.\n");
//panic("Need implementation\n"); //panic("Need implementation\n");
} }
void void
Opteron::clearConsoleInt() PC::clearConsoleInt()
{ {
warn_once("Don't know what interrupt to clear for console.\n"); warn_once("Don't know what interrupt to clear for console.\n");
//panic("Need implementation\n"); //panic("Need implementation\n");
} }
void void
Opteron::postPciInt(int line) PC::postPciInt(int line)
{ {
panic("Need implementation\n"); panic("Need implementation\n");
} }
void void
Opteron::clearPciInt(int line) PC::clearPciInt(int line)
{ {
panic("Need implementation\n"); panic("Need implementation\n");
} }
Addr Addr
Opteron::pciToDma(Addr pciAddr) const PC::pciToDma(Addr pciAddr) const
{ {
panic("Need implementation\n"); panic("Need implementation\n");
M5_DUMMY_RETURN M5_DUMMY_RETURN
@ -94,7 +94,7 @@ Opteron::pciToDma(Addr pciAddr) const
Addr Addr
Opteron::calcConfigAddr(int bus, int dev, int func) PC::calcConfigAddr(int bus, int dev, int func)
{ {
assert(func < 8); assert(func < 8);
assert(dev < 32); assert(dev < 32);
@ -102,8 +102,8 @@ Opteron::calcConfigAddr(int bus, int dev, int func)
return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11)); return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
} }
Opteron * PC *
OpteronParams::create() PCParams::create()
{ {
return new Opteron(this); return new PC(this);
} }

View file

@ -30,29 +30,29 @@
/** /**
* @file * @file
* Declaration of top level class for the Opteron platform chips. This class * Declaration of top level class for PC platform components. This class
* just retains pointers to all its children so the children can communicate. * just retains pointers to all its children so the children can communicate.
*/ */
#ifndef __DEV_Opteron_HH__ #ifndef __DEV_PC_HH__
#define __DEV_Opteron_HH__ #define __DEV_PC_HH__
#include "dev/platform.hh" #include "dev/platform.hh"
#include "params/Opteron.hh" #include "params/PC.hh"
class IdeController; class IdeController;
class System; class System;
class Opteron : public Platform class PC : public Platform
{ {
public: public:
/** Pointer to the system */ /** Pointer to the system */
System *system; System *system;
public: public:
typedef OpteronParams Params; typedef PCParams Params;
Opteron(const Params *p); PC(const Params *p);
/** /**
* Return the interrupting frequency to AlphaAccess * Return the interrupting frequency to AlphaAccess
@ -89,4 +89,4 @@ class Opteron : public Platform
virtual Addr calcConfigAddr(int bus, int dev, int func); virtual Addr calcConfigAddr(int bus, int dev, int func);
}; };
#endif // __DEV_OPTERON_HH__ #endif // __DEV_PC_HH__