X86: Change the Opteron platform to be the PC platform.
--HG-- extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
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6 changed files with 82 additions and 50 deletions
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@ -177,19 +177,12 @@ def makeLinuxX86System(mem_mode, mdesc = None):
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self.bridge.side_a = self.iobus.port
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.bridge.side_b = self.membus.port
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# Serial port and console
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self.console = SimConsole()
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self.com_1 = Uart8250()
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self.com_1.pio_addr = x86IOAddress(0x3f8)
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self.com_1.pio = self.iobus.port
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self.com_1.sim_console = self.console
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# Command line
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# Command line
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self.boot_osflags = 'earlyprintk=ttyS0'
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self.boot_osflags = 'earlyprintk=ttyS0'
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# Platform
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# Platform
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self.opteron = Opteron()
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self.pc = PC()
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self.opteron.attachIO(self.iobus)
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self.pc.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.intrctrl = IntrControl()
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@ -1,18 +0,0 @@
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
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from Uart import Uart8250
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from Platform import Platform
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from Pci import PciConfigAll
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from SimConsole import SimConsole
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class Opteron(Platform):
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type = 'Opteron'
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system = Param.System(Parent.any, "system")
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pciconfig = PciConfigAll()
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def attachIO(self, bus):
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self.pciconfig.pio = bus.default
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bus.responder_set = True
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bus.responder = self.pciconfig
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57
src/dev/x86/PC.py
Normal file
57
src/dev/x86/PC.py
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@ -0,0 +1,57 @@
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# Copyright (c) 2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
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from Uart import Uart8250
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from Platform import Platform
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from Pci import PciConfigAll
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from SimConsole import SimConsole
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port;
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class PC(Platform):
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type = 'PC'
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system = Param.System(Parent.any, "system")
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pciconfig = PciConfigAll()
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# Serial port and console
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console = SimConsole()
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com_1 = Uart8250()
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com_1.pio_addr = x86IOAddress(0x3f8)
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com_1.sim_console = console
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def attachIO(self, bus):
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self.com_1.pio = bus.port
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self.pciconfig.pio = bus.default
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bus.responder_set = True
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bus.responder = self.pciconfig
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@ -32,6 +32,6 @@
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Import('*')
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Import('*')
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if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
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if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
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SimObject('Opteron.py')
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SimObject('PC.py')
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Source('opteron.cc')
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Source('pc.cc')
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@ -29,7 +29,7 @@
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*/
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*/
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/** @file
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/** @file
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* Implementation of Opteron platform.
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* Implementation of PC platform.
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*/
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*/
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#include <deque>
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#include <deque>
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@ -39,13 +39,13 @@
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#include "arch/x86/x86_traits.hh"
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#include "arch/x86/x86_traits.hh"
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#include "cpu/intr_control.hh"
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#include "cpu/intr_control.hh"
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#include "dev/simconsole.hh"
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#include "dev/simconsole.hh"
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#include "dev/x86/opteron.hh"
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#include "dev/x86/pc.hh"
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#include "sim/system.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace std;
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using namespace TheISA;
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using namespace TheISA;
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Opteron::Opteron(const Params *p)
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PC::PC(const Params *p)
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: Platform(p), system(p->system)
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: Platform(p), system(p->system)
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{
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{
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// set the back pointer from the system to myself
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// set the back pointer from the system to myself
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@ -53,40 +53,40 @@ Opteron::Opteron(const Params *p)
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}
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}
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Tick
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Tick
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Opteron::intrFrequency()
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PC::intrFrequency()
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{
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{
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panic("Need implementation\n");
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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M5_DUMMY_RETURN
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}
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}
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void
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void
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Opteron::postConsoleInt()
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PC::postConsoleInt()
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{
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{
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warn_once("Don't know what interrupt to post for console.\n");
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warn_once("Don't know what interrupt to post for console.\n");
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//panic("Need implementation\n");
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//panic("Need implementation\n");
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}
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}
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void
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void
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Opteron::clearConsoleInt()
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PC::clearConsoleInt()
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{
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{
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warn_once("Don't know what interrupt to clear for console.\n");
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warn_once("Don't know what interrupt to clear for console.\n");
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//panic("Need implementation\n");
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//panic("Need implementation\n");
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}
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}
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void
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void
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Opteron::postPciInt(int line)
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PC::postPciInt(int line)
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{
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{
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panic("Need implementation\n");
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panic("Need implementation\n");
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}
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}
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void
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void
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Opteron::clearPciInt(int line)
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PC::clearPciInt(int line)
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{
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{
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panic("Need implementation\n");
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panic("Need implementation\n");
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}
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}
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Addr
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Addr
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Opteron::pciToDma(Addr pciAddr) const
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PC::pciToDma(Addr pciAddr) const
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{
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{
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panic("Need implementation\n");
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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M5_DUMMY_RETURN
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@ -94,7 +94,7 @@ Opteron::pciToDma(Addr pciAddr) const
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Addr
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Addr
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Opteron::calcConfigAddr(int bus, int dev, int func)
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PC::calcConfigAddr(int bus, int dev, int func)
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{
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{
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assert(func < 8);
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assert(func < 8);
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assert(dev < 32);
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assert(dev < 32);
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@ -102,8 +102,8 @@ Opteron::calcConfigAddr(int bus, int dev, int func)
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return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
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return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
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}
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}
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Opteron *
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PC *
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OpteronParams::create()
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PCParams::create()
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{
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{
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return new Opteron(this);
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return new PC(this);
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}
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}
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@ -30,29 +30,29 @@
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/**
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/**
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* @file
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* @file
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* Declaration of top level class for the Opteron platform chips. This class
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* Declaration of top level class for PC platform components. This class
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* just retains pointers to all its children so the children can communicate.
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* just retains pointers to all its children so the children can communicate.
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*/
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*/
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#ifndef __DEV_Opteron_HH__
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#ifndef __DEV_PC_HH__
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#define __DEV_Opteron_HH__
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#define __DEV_PC_HH__
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#include "dev/platform.hh"
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#include "dev/platform.hh"
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#include "params/Opteron.hh"
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#include "params/PC.hh"
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class IdeController;
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class IdeController;
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class System;
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class System;
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class Opteron : public Platform
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class PC : public Platform
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{
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{
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public:
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public:
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/** Pointer to the system */
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/** Pointer to the system */
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System *system;
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System *system;
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public:
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public:
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typedef OpteronParams Params;
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typedef PCParams Params;
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Opteron(const Params *p);
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PC(const Params *p);
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/**
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/**
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* Return the interrupting frequency to AlphaAccess
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* Return the interrupting frequency to AlphaAccess
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@ -89,4 +89,4 @@ class Opteron : public Platform
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virtual Addr calcConfigAddr(int bus, int dev, int func);
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virtual Addr calcConfigAddr(int bus, int dev, int func);
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};
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};
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#endif // __DEV_OPTERON_HH__
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#endif // __DEV_PC_HH__
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