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arm: change MISCREG_L2ERRSR to warn not fail

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Some newer binaries compiled for Versatile Express TC2 contain access
to implementation specific L2MERRSR registers. This causes an infinite
loop of undefined exceptions. This patch changes the behavior to "warn
not fail" to keep the workloads going.
This commit is contained in:
Dam Sunwoo 2014-08-13 06:57:36 -04:00
parent 74a4926fe0
commit b04d6c7c33
1 changed files with 2 additions and 2 deletions
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4
src/arch/arm/miscregs.cc
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@ -770,7 +770,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
// MISCREG_CPUMERRSR
bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")),
// MISCREG_L2MERRSR
bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")),
bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")),
// AArch64 registers (Op0=2)
// MISCREG_MDCCINT_EL1
@ -1330,7 +1330,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
// MISCREG_CPUMERRSR_EL1
bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")),
// MISCREG_L2MERRSR_EL1
bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")),
bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")),
// MISCREG_CBAR_EL1
bitset<NUM_MISCREG_INFOS>(string("0101010101000000001")),