stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
This commit is contained in:
Andreas Hansson
parent
5a1dea51d2
commit
b006ad26d4
116 changed files with 19019 additions and 20882 deletions
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@ -4,11 +4,11 @@ sim_seconds 1.907083 # Nu
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sim_ticks 1907083088000 # Number of ticks simulated
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final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 20030 # Simulator instruction rate (inst/s)
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host_op_rate 20030 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 680419212 # Simulator tick rate (ticks/s)
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host_inst_rate 20979 # Simulator instruction rate (inst/s)
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host_op_rate 20979 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 712669715 # Simulator tick rate (ticks/s)
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host_mem_usage 389460 # Number of bytes of host memory used
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host_seconds 2802.81 # Real time elapsed on the host
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host_seconds 2675.97 # Real time elapsed on the host
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sim_insts 56139550 # Number of instructions simulated
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sim_ops 56139550 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -563,8 +563,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks
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system.cpu.dcache.writebacks::total 837991 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits
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@ -605,10 +603,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500
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system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::total 3690574000 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses
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@ -631,11 +627,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency
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system.cpu.icache.tags.replacements 1471396 # number of replacements
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system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks.
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@ -694,8 +687,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks
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system.cpu.icache.writebacks::total 1471396 # number of writebacks
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses
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@ -722,7 +713,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974
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system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 339491 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks.
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@ -843,8 +833,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks
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system.cpu.l2cache.writebacks::total 76584 # number of writebacks
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system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses
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@ -883,10 +871,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500
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system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles
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system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses
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@ -917,11 +903,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency
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system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency
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system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency
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system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter.
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system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
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@ -1053,26 +1036,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 #
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system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
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system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
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system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
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system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
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system.iocache.demand_misses::total 173 # number of demand (read+write) misses
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system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
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system.iocache.overall_misses::total 173 # number of overall misses
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system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
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system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
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system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
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system.iocache.overall_misses::total 41725 # number of overall misses
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system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles
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system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles
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system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles
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system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles
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system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles
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system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles
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system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles
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system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles
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system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles
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system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles
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system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
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system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
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system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
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system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
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system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
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system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
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system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
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@ -1085,36 +1068,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145
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system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency
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system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency
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system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency
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system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency
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system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
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system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency
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system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency
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system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
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system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency
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system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.writebacks::writebacks 41512 # number of writebacks
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system.iocache.writebacks::total 41512 # number of writebacks
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system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
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system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
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system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
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system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
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system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
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system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
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system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
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system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
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system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
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system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles
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system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles
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system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
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@ -1127,11 +1108,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145
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system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency
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system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency
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system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
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system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
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system.membus.trans_dist::ReadReq 6930 # Transaction distribution
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system.membus.trans_dist::ReadResp 295608 # Transaction distribution
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system.membus.trans_dist::WriteReq 9623 # Transaction distribution
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@ -4,11 +4,11 @@ sim_seconds 1.929078 # Nu
|
|||
sim_ticks 1929077876500 # Number of ticks simulated
|
||||
final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 158135 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 158134 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5371969736 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 169237 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 169237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5749129790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 339544 # Number of bytes of host memory used
|
||||
host_seconds 359.10 # Real time elapsed on the host
|
||||
host_seconds 335.54 # Real time elapsed on the host
|
||||
sim_insts 56786201 # Number of instructions simulated
|
||||
sim_ops 56786201 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -746,8 +746,6 @@ system.cpu0.dcache.blocked::no_mshrs 111036 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 741086 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits
|
||||
|
|
@ -792,10 +790,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557
|
|||
system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -822,11 +818,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650
|
|||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 911237 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks.
|
||||
|
|
@ -884,8 +877,6 @@ system.cpu0.icache.blocked::no_mshrs 347 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 911237 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits
|
||||
|
|
@ -918,7 +909,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258
|
|||
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.branchPred.lookups 4129053 # Number of BP lookups
|
||||
system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted
|
||||
system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect
|
||||
|
|
@ -1352,8 +1342,6 @@ system.cpu1.dcache.blocked::no_mshrs 22564 # nu
|
|||
system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 79554 # number of writebacks
|
||||
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits
|
||||
|
|
@ -1398,10 +1386,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462
|
|||
system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1428,11 +1414,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694
|
|||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.tags.replacements 244089 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks.
|
||||
|
|
@ -1491,8 +1474,6 @@ system.cpu1.icache.blocked::no_mshrs 56 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 244089 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits
|
||||
|
|
@ -1525,7 +1506,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520
|
|||
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -1610,26 +1590,26 @@ system.iocache.ReadReq_misses::tsunami.ide 175 #
|
|||
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 175 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
|
||||
system.iocache.overall_misses::total 175 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
|
||||
system.iocache.overall_misses::total 41727 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1642,36 +1622,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000
|
|||
system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1684,11 +1662,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 345263 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65201.794559 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4034348 # Total number of references to valid blocks.
|
||||
|
|
@ -1879,8 +1856,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 81472 # number of writebacks
|
||||
system.l2c.writebacks::total 81472 # number of writebacks
|
||||
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1956,12 +1931,9 @@ system.l2c.overall_mshr_miss_latency::total 49061475524 #
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1471043500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30151000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 1501194500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2180387500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 660346500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 2840734000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3651431000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 690497500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 4341928500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1471043500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30151000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 1501194500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941646 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -2017,13 +1989,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 119350.368973
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 9565.672589 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 7193 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 297247 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13095 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.876794 # Nu
|
|||
sim_ticks 1876794488000 # Number of ticks simulated
|
||||
final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 164316 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5820514836 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 142986 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 142986 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5064945596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 335448 # Number of bytes of host memory used
|
||||
host_seconds 322.44 # Real time elapsed on the host
|
||||
host_seconds 370.55 # Real time elapsed on the host
|
||||
sim_insts 52982943 # Number of instructions simulated
|
||||
sim_ops 52982943 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -734,8 +734,6 @@ system.cpu.dcache.blocked::no_mshrs 133846 # nu
|
|||
system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 843569 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits
|
||||
|
|
@ -780,10 +778,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -810,11 +806,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 1074186 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks.
|
||||
|
|
@ -873,8 +866,6 @@ system.cpu.icache.blocked::no_mshrs 342 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1074186 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits
|
||||
|
|
@ -907,7 +898,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 338591 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks.
|
||||
|
|
@ -1040,8 +1030,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 76108 # number of writebacks
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses
|
||||
|
|
@ -1084,10 +1072,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002
|
|||
system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses
|
||||
|
|
@ -1122,11 +1108,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1259,26 +1242,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 #
|
|||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
||||
system.iocache.overall_misses::total 173 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
||||
system.iocache.overall_misses::total 41725 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1291,36 +1274,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451
|
|||
system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1333,11 +1314,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 296606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9599 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.843617 # Nu
|
|||
sim_ticks 1843616607000 # Number of ticks simulated
|
||||
final_tick 1843616607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 222443 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 222443 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5619525357 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 248643 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 248643 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6281412703 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 335188 # Number of bytes of host memory used
|
||||
host_seconds 328.07 # Real time elapsed on the host
|
||||
host_seconds 293.50 # Real time elapsed on the host
|
||||
sim_insts 72977545 # Number of instructions simulated
|
||||
sim_ops 72977545 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -644,8 +644,6 @@ system.cpu0.dcache.blocked::no_mshrs 58664 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.111823 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets 183.363636 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 836302 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 836302 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286455 # number of ReadReq MSHR hits
|
||||
|
|
@ -704,12 +702,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total 13534205301
|
|||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296833500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 314974000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 611807500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 374975500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 441435000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 816410500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 671809000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 756409000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428218000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 296833500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 314974000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 611807500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.077888 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.078352 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037572 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -747,13 +742,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28101.652148
|
|||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220530.089153 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230187.538367 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223964.992390 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226780.694444 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225818.151261 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224653.697654 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225199.936928 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 99775.966387 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 93547.371547 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96469.173762 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 969392 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.185439 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 43108744 # Total number of references to valid blocks.
|
||||
|
|
@ -846,8 +837,6 @@ system.cpu0.icache.blocked::no_mshrs 386 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.572539 # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 969392 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 969392 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 21576 # number of ReadReq MSHR hits
|
||||
|
|
@ -892,7 +881,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624
|
|||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -1418,26 +1406,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 #
|
|||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
||||
system.iocache.overall_misses::total 173 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
||||
system.iocache.overall_misses::total 41725 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 9857962 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 9857962 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::tsunami.ide 1957317692 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 1957317692 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 9857962 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 9857962 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 9857962 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 9857962 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 1967175654 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1967175654 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 1967175654 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1967175654 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1450,53 +1438,50 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306
|
|||
system.iocache.ReadReq_avg_miss_latency::total 56982.439306 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 56982.439306 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 56982.439306 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 56982.439306 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 56982.439306 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 47146.211001 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 47146.211001 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 68 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 15504 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 15504 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 68 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 68 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 68 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 68 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 15572 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 15572 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 15572 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 15572 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6457962 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 6457962 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1181451904 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 1181451904 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 6457962 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 6457962 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 6457962 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 6457962 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 1187909866 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1187909866 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 1187909866 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1187909866 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 0.393064 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.373123 # mshr miss rate for WriteLineReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::total 0.373123 # mshr miss rate for WriteLineReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 0.393064 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 0.393064 # mshr miss rate for overall accesses
|
||||
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 0.373206 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 0.373206 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::total 94970.029412 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76203.038184 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76203.038184 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 94970.029412 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 94970.029412 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 337717 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65421.749224 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4019101 # Total number of references to valid blocks.
|
||||
|
|
@ -1716,8 +1701,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 75320 # number of writebacks
|
||||
system.l2c.writebacks::total 75320 # number of writebacks
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses
|
||||
|
|
@ -1778,12 +1761,9 @@ system.l2c.overall_mshr_miss_latency::total 8481752004 #
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 280001500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 297523000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 577524500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 356232500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418765500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 774998000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 636234000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716288500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 1352522500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 280001500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 297523000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 577524500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.681818 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.136364 # mshr miss rate for SCUpgradeReq accesses
|
||||
|
|
@ -1833,13 +1813,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 121109.061370
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208024.888559 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 213125.358166 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210621.626550 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218681.706568 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212463.470320 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215277.222222 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213860.168067 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212737.897238 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 213264.348786 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94118.151261 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88364.419364 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 91063.465784 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 7144 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 295030 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9812 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.848878 # Nu
|
|||
sim_ticks 2848878048000 # Number of ticks simulated
|
||||
final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 194660 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 620428 # Number of bytes of host memory used
|
||||
host_seconds 651.58 # Real time elapsed on the host
|
||||
host_inst_rate 186843 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 226247 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4196685224 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 620168 # Number of bytes of host memory used
|
||||
host_seconds 678.84 # Real time elapsed on the host
|
||||
sim_insts 126836472 # Number of instructions simulated
|
||||
sim_ops 153585571 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -694,8 +694,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 757698 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
|
||||
|
|
@ -746,10 +744,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000
|
|||
system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -782,11 +778,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251
|
|||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 2042425 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
|
||||
|
|
@ -845,8 +838,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 2042425 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
|
||||
|
|
@ -885,7 +876,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304
|
|||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
|
||||
system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
|
||||
system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1080,8 +1070,6 @@ system.cpu0.l2cache.blocked::no_mshrs 1 # nu
|
|||
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
|
||||
|
|
@ -1162,11 +1150,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429
|
|||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6445890500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6971910500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1224,12 +1210,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222
|
|||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1622,8 +1605,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 155125 # number of writebacks
|
||||
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
|
||||
|
|
@ -1674,10 +1655,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500
|
|||
system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1710,11 +1689,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936
|
|||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.tags.replacements 856657 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
|
||||
|
|
@ -1773,8 +1749,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 856657 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
|
||||
|
|
@ -1813,7 +1787,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857
|
|||
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
|
||||
system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
|
||||
system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -2010,8 +1983,6 @@ system.cpu1.l2cache.blocked::no_mshrs 1 # nu
|
|||
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
|
||||
|
|
@ -2094,11 +2065,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741
|
|||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2158,12 +2127,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946
|
|||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -2334,26 +2300,26 @@ system.iocache.ReadReq_misses::realview.ide 243 #
|
|||
system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 243 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 243 # number of overall misses
|
||||
system.iocache.overall_misses::total 243 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36467 # number of overall misses
|
||||
system.iocache.overall_misses::total 36467 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -2366,36 +2332,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897
|
|||
system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -2408,11 +2372,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 132278 # number of replacements
|
||||
system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
|
||||
|
|
@ -2707,8 +2670,6 @@ system.l2c.blocked::no_mshrs 9 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102335 # number of writebacks
|
||||
system.l2c.writebacks::total 102335 # number of writebacks
|
||||
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -2818,14 +2779,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4740559503 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195045002 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 4935604505 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10609656010 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5869096507 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507159005 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 11572801015 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 312114003 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 6637196510 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -2911,15 +2869,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 39041 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 216336 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 31035 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu
|
|||
sim_ticks 2858505242500 # Number of ticks simulated
|
||||
final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 194204 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 234807 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4961098243 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 583728 # Number of bytes of host memory used
|
||||
host_seconds 576.18 # Real time elapsed on the host
|
||||
host_inst_rate 187730 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 226980 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4795719535 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 583724 # Number of bytes of host memory used
|
||||
host_seconds 596.05 # Real time elapsed on the host
|
||||
sim_insts 111897168 # Number of instructions simulated
|
||||
sim_ops 135292215 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -651,8 +651,6 @@ system.cpu.dcache.blocked::no_mshrs 23 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.304348 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 699681 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 699681 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76216 # number of ReadReq MSHR hits
|
||||
|
|
@ -701,10 +699,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27438355500
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 27438355500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277881000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277881000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5085127500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5085127500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363008500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363008500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6277881000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6277881000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017764 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017764 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015869 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -735,11 +731,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 2894371 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks.
|
||||
|
|
@ -798,8 +791,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2894371 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2894371 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894895 # number of ReadReq MSHR misses
|
||||
|
|
@ -838,7 +829,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108
|
|||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 96490 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks.
|
||||
|
|
@ -1018,8 +1008,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 88112 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 88112 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1089,11 +1077,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 19994125000
|
|||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 427218000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888707000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315925000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4767887000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4767887000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656594000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083812000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888707000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6315925000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001612 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1143,12 +1129,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1316,26 +1299,26 @@ system.iocache.ReadReq_misses::realview.ide 234 #
|
|||
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 234 # number of overall misses
|
||||
system.iocache.overall_misses::total 234 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36458 # number of overall misses
|
||||
system.iocache.overall_misses::total 36458 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 29059377 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 29059377 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 29059377 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 29059377 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1348,36 +1331,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795
|
|||
system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 124185.371795 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 124185.371795 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 17359377 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 17359377 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 17359377 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 17359377 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1390,11 +1371,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 34891 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 72400 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27583 # Transaction distribution
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 47.535940 # Nu
|
|||
sim_ticks 47535940136000 # Number of ticks simulated
|
||||
final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 225035 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 264677 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11911388135 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 769700 # Number of bytes of host memory used
|
||||
host_seconds 3990.80 # Real time elapsed on the host
|
||||
host_inst_rate 200561 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 235891 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 10615931561 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 769436 # Number of bytes of host memory used
|
||||
host_seconds 4477.79 # Real time elapsed on the host
|
||||
sim_insts 898069628 # Number of instructions simulated
|
||||
sim_ops 1056270581 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -647,10 +647,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481
|
|||
system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses
|
||||
|
|
@ -663,10 +663,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543
|
|||
system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles
|
||||
|
|
@ -679,10 +679,10 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500
|
|||
system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -695,10 +695,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024
|
|||
system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 170439683 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 170439683 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 171406455 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 171406455 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses
|
||||
|
|
@ -711,10 +711,10 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613
|
|||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036104 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039761 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency
|
||||
|
|
@ -727,18 +727,16 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058
|
|||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 5972043 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits
|
||||
|
|
@ -751,10 +749,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits
|
||||
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits
|
||||
system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits
|
||||
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits
|
||||
system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits
|
||||
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits
|
||||
system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits
|
||||
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses
|
||||
system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses
|
||||
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses
|
||||
|
|
@ -767,10 +765,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -791,16 +789,14 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000
|
|||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -813,10 +809,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency
|
||||
|
|
@ -831,17 +827,14 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412
|
|||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 10516028 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks.
|
||||
|
|
@ -900,8 +893,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 10516028 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses
|
||||
|
|
@ -940,7 +931,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392
|
|||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued
|
||||
system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified
|
||||
system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1158,8 +1148,6 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.unused_prefetches 49728 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu0.l2cache.writebacks::writebacks 1630983 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 1630983 # number of writebacks
|
||||
|
|
@ -1255,11 +1243,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241
|
|||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788797000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12784952000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5603650500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5603650500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788797000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12784952000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1325,12 +1311,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938
|
|||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1653,10 +1636,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906
|
|||
system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses
|
||||
|
|
@ -1669,10 +1652,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945
|
|||
system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles
|
||||
|
|
@ -1685,10 +1668,10 @@ system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500
|
|||
system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -1701,10 +1684,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851
|
|||
system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses
|
||||
|
|
@ -1717,10 +1700,10 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981
|
|||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency
|
||||
|
|
@ -1733,18 +1716,16 @@ system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501
|
|||
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 5011891 # number of writebacks
|
||||
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits
|
||||
|
|
@ -1757,10 +1738,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165
|
|||
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits
|
||||
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits
|
||||
system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits
|
||||
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits
|
||||
system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits
|
||||
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits
|
||||
system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits
|
||||
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses
|
||||
system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses
|
||||
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses
|
||||
|
|
@ -1773,10 +1754,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780
|
|||
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -1797,16 +1778,14 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500
|
|||
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1819,10 +1798,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139
|
|||
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency
|
||||
|
|
@ -1837,17 +1816,14 @@ system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022
|
|||
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.tags.replacements 8449872 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks.
|
||||
|
|
@ -1906,8 +1882,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 8449872 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses
|
||||
|
|
@ -1946,7 +1920,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624
|
|||
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued
|
||||
system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified
|
||||
system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -2162,8 +2135,6 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.unused_prefetches 46108 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu1.l2cache.writebacks::writebacks 1173247 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 1173247 # number of writebacks
|
||||
|
|
@ -2256,11 +2227,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348
|
|||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860931500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 873205500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2324,12 +2293,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747
|
|||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -2491,11 +2457,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115901 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8877 # number of overall misses
|
||||
system.iocache.overall_misses::total 8917 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115861 # number of overall misses
|
||||
system.iocache.overall_misses::total 115901 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles
|
||||
|
|
@ -2504,11 +2470,11 @@ system.iocache.WriteReq_miss_latency::total 369000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -2517,11 +2483,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -2543,19 +2509,17 @@ system.iocache.WriteReq_avg_miss_latency::total 123000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106951 # number of writebacks
|
||||
system.iocache.writebacks::total 106951 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -2566,11 +2530,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -2579,11 +2543,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 219000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2605,12 +2569,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 73000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 1387428 # number of replacements
|
||||
system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks.
|
||||
|
|
@ -2939,8 +2902,6 @@ system.l2c.blocked::no_mshrs 13 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs 74.692308 # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 1075915 # number of writebacks
|
||||
system.l2c.writebacks::total 1075915 # number of writebacks
|
||||
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 164 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -3071,14 +3032,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5220688053
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10320500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 728734017 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 11857408570 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5073884538 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 907395547 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 5981280085 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10294572591 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5220688053 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10320500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1636129564 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 17838688655 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728734017 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 11857408570 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -3176,15 +3134,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 91289 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 902614 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 38789 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.660653 # Nu
|
|||
sim_ticks 51660652947000 # Number of ticks simulated
|
||||
final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 204210 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 239956 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11350998190 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 682908 # Number of bytes of host memory used
|
||||
host_seconds 4551.20 # Real time elapsed on the host
|
||||
host_inst_rate 286668 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 336848 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15934426663 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 682904 # Number of bytes of host memory used
|
||||
host_seconds 3242.08 # Real time elapsed on the host
|
||||
sim_insts 929398934 # Number of instructions simulated
|
||||
sim_ops 1092086880 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -604,10 +604,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 313786004 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 313786004 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 314301494 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 314301494 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 314638081 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses
|
||||
|
|
@ -620,10 +620,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 10601209 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 10601209 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 12022090 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 12022090 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 13262190 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles
|
||||
|
|
@ -634,10 +634,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500
|
|||
system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 325526040000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 325526040000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 325526040000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 325526040000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -650,10 +650,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 324387213 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 324387213 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 326323584 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 326323584 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses
|
||||
|
|
@ -666,10 +666,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032681 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032681 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036841 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036841 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency
|
||||
|
|
@ -680,18 +680,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259
|
|||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30706.501494 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8312311 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits
|
||||
|
|
@ -702,10 +700,10 @@ system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166
|
|||
system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2620111 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2620111 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2620111 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2620111 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses
|
||||
|
|
@ -718,10 +716,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438
|
|||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 7981098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 7981098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9394451 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9394451 # number of overall MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -740,16 +738,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 206893714000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 233795004500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6191865500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6191865500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12389494000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12389494000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -762,10 +758,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024604 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.024604 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028789 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.028789 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency
|
||||
|
|
@ -778,17 +774,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346
|
|||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 24339101 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks.
|
||||
|
|
@ -847,8 +840,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 24339101 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 24339101 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24339623 # number of ReadReq MSHR misses
|
||||
|
|
@ -887,7 +878,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182
|
|||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1529682 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks.
|
||||
|
|
@ -1080,8 +1070,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1293856 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1293856 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1157,11 +1145,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028
|
|||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776326000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712400000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5803513500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5803513500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11579839500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17515913500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776326000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712400000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008952 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1217,12 +1203,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1379,11 +1362,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8879 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115543 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8839 # number of overall misses
|
||||
system.iocache.overall_misses::total 8879 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115503 # number of overall misses
|
||||
system.iocache.overall_misses::total 115543 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles
|
||||
|
|
@ -1392,11 +1375,11 @@ system.iocache.WriteReq_miss_latency::total 351000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1644126101 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1649547101 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1644126101 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1649547101 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1405,11 +1388,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -1431,19 +1414,17 @@ system.iocache.WriteReq_avg_miss_latency::total 117000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 185780.729925 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 185780.729925 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106630 # number of writebacks
|
||||
system.iocache.writebacks::total 106630 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -1454,11 +1435,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -1467,11 +1448,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 201000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1202176101 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1205597101 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1202176101 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1205597101 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1493,12 +1474,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 67000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 86006 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 535040 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33706 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu
|
|||
sim_ticks 51327139864000 # Number of ticks simulated
|
||||
final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 122613 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 144072 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7419967145 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 687012 # Number of bytes of host memory used
|
||||
host_seconds 6917.44 # Real time elapsed on the host
|
||||
host_inst_rate 109720 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 128923 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6639754669 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 687008 # Number of bytes of host memory used
|
||||
host_seconds 7730.28 # Real time elapsed on the host
|
||||
sim_insts 848164321 # Number of instructions simulated
|
||||
sim_ops 996610207 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -718,7 +718,7 @@ system.cpu.itb.accesses 357169890 # DT
|
|||
system.cpu.numCycles 1631144067 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken
|
||||
|
|
@ -732,21 +732,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 873 #
|
|||
system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle
|
||||
system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking
|
||||
|
|
@ -756,27 +756,27 @@ system.cpu.decode.BranchMispred 3814526 # Nu
|
|||
system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads.
|
||||
|
|
@ -788,11 +788,11 @@ system.cpu.iq.iqSquashedInstsIssued 3378731 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle
|
||||
|
|
@ -804,7 +804,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available
|
||||
|
|
@ -877,7 +877,7 @@ system.cpu.iq.FU_type_0::total 1045735608 # Ty
|
|||
system.cpu.iq.rate 0.641106 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads
|
||||
|
|
@ -894,7 +894,7 @@ system.cpu.iew.lsq.thread0.squashedStores 6061186 # N
|
|||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking
|
||||
|
|
@ -928,11 +928,11 @@ system.cpu.iew.wb_fanout 0.618086 # av
|
|||
system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle
|
||||
|
|
@ -944,7 +944,7 @@ system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 848164321 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -991,10 +991,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 2588836198 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 2588836134 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 2108972650 # The number of ROB writes
|
||||
system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 848164321 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated
|
||||
|
|
@ -1008,7 +1008,7 @@ system.cpu.fp_regfile_reads 1462624 # nu
|
|||
system.cpu.fp_regfile_writes 780384 # number of floating regfile writes
|
||||
system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.replacements 9706309 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
|
||||
|
|
@ -1038,10 +1038,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 275804158 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 276127624 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses
|
||||
|
|
@ -1054,10 +1054,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 22005420 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 23239410 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles
|
||||
|
|
@ -1068,10 +1068,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000
|
|||
system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -1084,10 +1084,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses
|
||||
|
|
@ -1100,10 +1100,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency
|
||||
|
|
@ -1114,18 +1114,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553
|
|||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 7511281 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits
|
||||
|
|
@ -1136,10 +1134,10 @@ system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130
|
|||
system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 13703391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 13703391 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 13703391 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses
|
||||
|
|
@ -1152,10 +1150,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409
|
|||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 7131279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 7131279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 8295216 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 8295216 # number of overall MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -1174,16 +1172,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1196,10 +1192,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency
|
||||
|
|
@ -1212,17 +1208,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311
|
|||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 15141033 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
|
||||
|
|
@ -1281,8 +1274,6 @@ system.cpu.icache.blocked::no_mshrs 1460 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 15141033 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 15141033 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits
|
||||
|
|
@ -1327,7 +1318,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724
|
|||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1146896 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks.
|
||||
|
|
@ -1522,8 +1512,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 961909 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 961909 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
|
||||
|
|
@ -1599,11 +1587,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 95507463453
|
|||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770895500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189659000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836145500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836145500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607041000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025804500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770895500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189659000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006451 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1659,12 +1645,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1821,11 +1804,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115518 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8814 # number of overall misses
|
||||
system.iocache.overall_misses::total 8854 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115478 # number of overall misses
|
||||
system.iocache.overall_misses::total 115518 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles
|
||||
|
|
@ -1834,11 +1817,11 @@ system.iocache.WriteReq_miss_latency::total 351000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1847,11 +1830,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -1873,19 +1856,17 @@ system.iocache.WriteReq_avg_miss_latency::total 117000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106630 # number of writebacks
|
||||
system.iocache.writebacks::total 106630 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -1896,11 +1877,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -1909,11 +1890,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 201000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1935,12 +1916,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 67000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 410008 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
|
||||
|
|
@ -1986,7 +1966,7 @@ system.membus.reqLayer0.occupancy 103925500 # La
|
|||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu
|
|||
sim_ticks 51327139864000 # Number of ticks simulated
|
||||
final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 139665 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164109 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8451911555 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 688288 # Number of bytes of host memory used
|
||||
host_seconds 6072.84 # Real time elapsed on the host
|
||||
host_inst_rate 139449 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163855 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8438816943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 688284 # Number of bytes of host memory used
|
||||
host_seconds 6082.27 # Real time elapsed on the host
|
||||
sim_insts 848164321 # Number of instructions simulated
|
||||
sim_ops 996610207 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -579,7 +579,7 @@ system.cpu.itb.accesses 357169890 # DT
|
|||
system.cpu.numCycles 1631144067 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken
|
||||
|
|
@ -593,21 +593,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 873 #
|
|||
system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle
|
||||
system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking
|
||||
|
|
@ -617,27 +617,27 @@ system.cpu.decode.BranchMispred 3814526 # Nu
|
|||
system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads.
|
||||
|
|
@ -649,11 +649,11 @@ system.cpu.iq.iqSquashedInstsIssued 3378731 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle
|
||||
|
|
@ -665,7 +665,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available
|
||||
|
|
@ -738,7 +738,7 @@ system.cpu.iq.FU_type_0::total 1045735608 # Ty
|
|||
system.cpu.iq.rate 0.641106 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads
|
||||
|
|
@ -755,7 +755,7 @@ system.cpu.iew.lsq.thread0.squashedStores 6061186 # N
|
|||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking
|
||||
|
|
@ -789,11 +789,11 @@ system.cpu.iew.wb_fanout 0.618086 # av
|
|||
system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle
|
||||
|
|
@ -805,7 +805,7 @@ system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 848164321 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -852,10 +852,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 2588836198 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 2588836134 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 2108972650 # The number of ROB writes
|
||||
system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 848164321 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated
|
||||
|
|
@ -869,7 +869,7 @@ system.cpu.fp_regfile_reads 1462624 # nu
|
|||
system.cpu.fp_regfile_writes 780384 # number of floating regfile writes
|
||||
system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.replacements 9706309 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
|
||||
|
|
@ -899,10 +899,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 275804158 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 276127624 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses
|
||||
|
|
@ -915,10 +915,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 22005420 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 23239410 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles
|
||||
|
|
@ -929,10 +929,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000
|
|||
system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -945,10 +945,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses
|
||||
|
|
@ -961,10 +961,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency
|
||||
|
|
@ -975,18 +975,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553
|
|||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 7511281 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits
|
||||
|
|
@ -997,10 +995,10 @@ system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130
|
|||
system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 13703391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 13703391 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 13703391 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses
|
||||
|
|
@ -1013,10 +1011,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409
|
|||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 7131279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 7131279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 8295216 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 8295216 # number of overall MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -1035,16 +1033,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1057,10 +1053,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency
|
||||
|
|
@ -1073,17 +1069,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311
|
|||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 15141033 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
|
||||
|
|
@ -1142,8 +1135,6 @@ system.cpu.icache.blocked::no_mshrs 1460 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 15141033 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 15141033 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits
|
||||
|
|
@ -1188,7 +1179,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724
|
|||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1146896 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks.
|
||||
|
|
@ -1383,8 +1373,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 961909 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 961909 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
|
||||
|
|
@ -1460,11 +1448,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 95507463453
|
|||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770895500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189659000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836145500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836145500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607041000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025804500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770895500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189659000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006451 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1520,12 +1506,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1682,11 +1665,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115518 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8814 # number of overall misses
|
||||
system.iocache.overall_misses::total 8854 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115478 # number of overall misses
|
||||
system.iocache.overall_misses::total 115518 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles
|
||||
|
|
@ -1695,11 +1678,11 @@ system.iocache.WriteReq_miss_latency::total 351000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1708,11 +1691,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -1734,19 +1717,17 @@ system.iocache.WriteReq_avg_miss_latency::total 117000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106630 # number of writebacks
|
||||
system.iocache.writebacks::total 106630 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -1757,11 +1738,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -1770,11 +1751,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 201000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1796,12 +1777,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 67000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 410008 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
|
||||
|
|
@ -1847,7 +1827,7 @@ system.membus.reqLayer0.occupancy 103925500 # La
|
|||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
|
|||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1780456 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2092420 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 92650032032 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679092 # Number of bytes of host memory used
|
||||
host_seconds 551.66 # Real time elapsed on the host
|
||||
host_inst_rate 1195823 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1405350 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62227318824 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 678332 # Number of bytes of host memory used
|
||||
host_seconds 821.36 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -300,10 +300,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330608768 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330945053 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses
|
||||
|
|
@ -316,10 +316,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 10157717 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11404487 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -332,10 +332,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
|
||||
|
|
@ -348,21 +348,18 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8917390 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 14265253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
|
||||
|
|
@ -409,11 +406,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14265253 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1725806 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
|
||||
|
|
@ -555,11 +549,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1507080 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -670,11 +661,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115517 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
|
||||
system.iocache.overall_misses::total 8853 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115477 # number of overall misses
|
||||
system.iocache.overall_misses::total 115517 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -683,11 +674,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -707,11 +698,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524946 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 47.256536 # Nu
|
|||
sim_ticks 47256535705500 # Number of ticks simulated
|
||||
final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1671940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1966949 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 80984002716 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 693668 # Number of bytes of host memory used
|
||||
host_seconds 583.53 # Real time elapsed on the host
|
||||
host_inst_rate 1118024 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1315296 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 54153885278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 690972 # Number of bytes of host memory used
|
||||
host_seconds 872.63 # Real time elapsed on the host
|
||||
sim_insts 975625723 # Number of instructions simulated
|
||||
sim_ops 1147772483 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -331,10 +331,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285
|
|||
system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 165871488 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 165871488 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 166085900 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 166085900 # number of overall hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 166131177 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 166131177 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 166345589 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 166345589 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses
|
||||
|
|
@ -347,10 +347,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361
|
|||
system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 4777518 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 4777518 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 5552076 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 5552076 # number of overall misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 5600711 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 5600711 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 6375269 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 6375269 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -363,10 +363,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646
|
|||
system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 171731888 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 171731888 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 172720858 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 172720858 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses
|
||||
|
|
@ -379,21 +379,18 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858
|
|||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032348 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.032348 # miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032613 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.032613 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036911 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.036911 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 6248192 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 5479450 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks.
|
||||
|
|
@ -440,11 +437,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 5479450 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
||||
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -590,11 +584,8 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -863,10 +854,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470
|
|||
system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 162001697 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 162001697 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 162189982 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 162189982 # number of overall hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 162066607 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 162066607 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 162254892 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 162254892 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses
|
||||
|
|
@ -879,10 +870,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888
|
|||
system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 4833784 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 4833784 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 5624082 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 5624082 # number of overall misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 5269627 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 5269627 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 6059925 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 6059925 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -895,10 +886,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358
|
|||
system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 167336234 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 167336234 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 168314817 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 168314817 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses
|
||||
|
|
@ -911,21 +902,18 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062
|
|||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033514 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.033514 # miss rate for overall accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031491 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.031491 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036004 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.036004 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 5963482 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.icache.tags.replacements 4804881 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks.
|
||||
|
|
@ -972,11 +960,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 4804881 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
||||
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1123,11 +1108,8 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1237,11 +1219,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8927 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115655 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8887 # number of overall misses
|
||||
system.iocache.overall_misses::total 8927 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115615 # number of overall misses
|
||||
system.iocache.overall_misses::total 115655 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1250,11 +1232,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -1274,11 +1256,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106694 # number of writebacks
|
||||
system.iocache.writebacks::total 106694 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 1766126 # number of replacements
|
||||
system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks.
|
||||
|
|
@ -1483,11 +1462,8 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 1473799 # number of writebacks
|
||||
system.l2c.writebacks::total 1473799 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 82185 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 568654 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 38847 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
|
|||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1770185 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2080350 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 92115569363 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 676500 # Number of bytes of host memory used
|
||||
host_seconds 554.86 # Real time elapsed on the host
|
||||
host_inst_rate 1114977 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1310339 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 58020354238 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 675736 # Number of bytes of host memory used
|
||||
host_seconds 880.92 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -300,10 +300,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330608768 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330945053 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses
|
||||
|
|
@ -316,10 +316,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 10157717 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11404487 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -332,10 +332,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
|
||||
|
|
@ -348,21 +348,18 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8917390 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 14265253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
|
||||
|
|
@ -409,11 +406,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14265253 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1725806 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
|
||||
|
|
@ -555,11 +549,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1507080 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -670,11 +661,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115517 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
|
||||
system.iocache.overall_misses::total 8853 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115477 # number of overall misses
|
||||
system.iocache.overall_misses::total 115517 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -683,11 +674,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -707,11 +698,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524946 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 47.460623 # Nu
|
|||
sim_ticks 47460623015500 # Number of ticks simulated
|
||||
final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 731783 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 860761 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39683148028 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 744736 # Number of bytes of host memory used
|
||||
host_seconds 1195.99 # Real time elapsed on the host
|
||||
host_inst_rate 734945 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 864481 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39854660745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 745756 # Number of bytes of host memory used
|
||||
host_seconds 1190.84 # Real time elapsed on the host
|
||||
sim_insts 875204273 # Number of instructions simulated
|
||||
sim_ops 1029460892 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -646,10 +646,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375
|
|||
system.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 1814831 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 152875582 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 152875582 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 153075138 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 153075138 # number of overall hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 153056972 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 153056972 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 153256528 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 153256528 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 2983943 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 2983943 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 1350734 # number of WriteReq misses
|
||||
|
|
@ -662,10 +662,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 159632
|
|||
system.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 4954267 # number of overall misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 5084807 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 5084807 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 5704397 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 5704397 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles
|
||||
|
|
@ -678,10 +678,10 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000
|
|||
system.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 128993802000 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 128993802000 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 128993802000 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 128993802000 # number of overall miss cycles
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -694,10 +694,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007
|
|||
system.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 158141779 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 158141779 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 158960925 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 158960925 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses
|
||||
|
|
@ -710,10 +710,10 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537
|
|||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032153 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.032153 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.035886 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.035886 # miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency
|
||||
|
|
@ -726,18 +726,16 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967
|
|||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25368.475539 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 25368.475539 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.047795 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 22613.047795 # average overall miss latency
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 5459134 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits
|
||||
|
|
@ -762,10 +760,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039170 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::total 5039170 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5657616 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::total 5657616 # number of overall MSHR misses
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -786,16 +784,14 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000
|
|||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 121748812000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 121748812000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136627701500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 136627701500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5439516500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5439516500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -808,10 +804,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::total 0.031865 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035591 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.035591 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency
|
||||
|
|
@ -826,17 +822,14 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800
|
|||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24160.489128 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24160.489128 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24149.341613 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24149.341613 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93183.891801 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93183.891801 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 5000286 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks.
|
||||
|
|
@ -895,8 +888,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 5000286 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 5000286 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5000799 # number of ReadReq MSHR misses
|
||||
|
|
@ -935,7 +926,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493
|
|||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7383328 # number of hwpf issued
|
||||
system.cpu0.l2cache.prefetcher.pfIdentified 7383330 # number of prefetch candidates identified
|
||||
system.cpu0.l2cache.prefetcher.pfBufferHit 1 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1149,8 +1139,6 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.unused_prefetches 39383 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 1473434 # number of writebacks
|
||||
|
|
@ -1233,11 +1221,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 98500032601
|
|||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5203415000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10834186500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5090437000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5090437000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10293852000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15924623500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5203415000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10834186500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043899 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1301,12 +1287,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834
|
|||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89139.257204 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106741.805338 # average overall mshr uncacheable latency
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1634,10 +1617,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683
|
|||
system.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 142761779 # number of overall hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 142736138 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 142736138 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 142907237 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 142907237 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses
|
||||
|
|
@ -1650,10 +1633,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519
|
|||
system.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 4814576 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 4814576 # number of overall misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 4671770 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 4671770 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 5298071 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 5298071 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45279528500 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_miss_latency::total 45279528500 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 30099423000 # number of WriteReq miss cycles
|
||||
|
|
@ -1666,10 +1649,10 @@ system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500
|
|||
system.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::cpu1.data 93474799500 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_latency::total 93474799500 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::cpu1.data 93474799500 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_latency::total 93474799500 # number of overall miss cycles
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -1682,10 +1665,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202
|
|||
system.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::cpu1.data 147407908 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses::total 147407908 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 148205308 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 148205308 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses
|
||||
|
|
@ -1698,10 +1681,10 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098
|
|||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031693 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.031693 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035748 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.035748 # miss rate for overall accesses
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency
|
||||
|
|
@ -1714,18 +1697,16 @@ system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709
|
|||
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20008.433527 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_miss_latency::total 20008.433527 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17643.176073 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_miss_latency::total 17643.176073 # average overall miss latency
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 5111729 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 5111729 # number of writebacks
|
||||
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16692 # number of ReadReq MSHR hits
|
||||
|
|
@ -1750,10 +1731,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540
|
|||
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4654676 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.demand_mshr_misses::total 4654676 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5280977 # number of overall MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_misses::total 5280977 # number of overall MSHR misses
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -1774,16 +1755,14 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500
|
|||
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 87347321500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency::total 87347321500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101627300000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency::total 101627300000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1460511000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1460511000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1796,10 +1775,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071
|
|||
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031577 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031577 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency
|
||||
|
|
@ -1814,17 +1793,14 @@ system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848
|
|||
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18765.499790 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18765.499790 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19244.033822 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19244.033822 # average overall mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82032.745450 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82032.745450 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.tags.replacements 4920276 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks.
|
||||
|
|
@ -1882,8 +1858,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 4920276 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 4920276 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4920793 # number of ReadReq MSHR misses
|
||||
|
|
@ -1922,7 +1896,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364
|
|||
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7108517 # number of hwpf issued
|
||||
system.cpu1.l2cache.prefetcher.pfIdentified 7108606 # number of prefetch candidates identified
|
||||
system.cpu1.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -2132,8 +2105,6 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.unused_prefetches 39620 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 1103180 # number of writebacks
|
||||
|
|
@ -2218,11 +2189,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 95457897080
|
|||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1390451500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1404390000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1502902000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1502902000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2893353500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1390451500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1404390000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041059 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2286,12 +2255,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452
|
|||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78097.702763 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78396.226415 # average overall mshr uncacheable latency
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -2451,11 +2417,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8919 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115607 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115647 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8879 # number of overall misses
|
||||
system.iocache.overall_misses::total 8919 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115607 # number of overall misses
|
||||
system.iocache.overall_misses::total 115647 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles
|
||||
|
|
@ -2464,11 +2430,11 @@ system.iocache.WriteReq_miss_latency::total 369000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15227361857 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15232928857 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15227361857 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15232928857 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -2477,11 +2443,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115607 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115647 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115607 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115647 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -2503,19 +2469,17 @@ system.iocache.WriteReq_avg_miss_latency::total 123000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 131719.187329 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 131719.187329 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106693 # number of writebacks
|
||||
system.iocache.writebacks::total 106693 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -2526,11 +2490,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115607 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115647 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115607 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115647 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236399949 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1239747949 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -2539,11 +2503,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 219000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8204144644 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8204144644 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9440544593 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9444111593 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9440544593 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9444111593 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2565,12 +2529,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 73000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 1288575 # number of replacements
|
||||
system.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 5304464 # Total number of references to valid blocks.
|
||||
|
|
@ -2897,8 +2860,6 @@ system.l2c.blocked::no_mshrs 25 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 1038944 # number of writebacks
|
||||
system.l2c.writebacks::total 1038944 # number of writebacks
|
||||
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 98 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -3026,14 +2987,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4673220523
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1233601518 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 10773300041 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4598373544 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1348007106 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 5946380650 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9271594067 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4673220523 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2581608624 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 16719680691 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1233601518 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 10773300041 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275559 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -3131,15 +3089,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80056.540977 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69295.670037 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 90220.331804 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 81394 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 801457 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 38017 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.759374 # Nu
|
|||
sim_ticks 51759374264500 # Number of ticks simulated
|
||||
final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1125548 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1322684 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 69608471837 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 675480 # Number of bytes of host memory used
|
||||
host_seconds 743.58 # Real time elapsed on the host
|
||||
host_inst_rate 729832 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 857659 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45135767006 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 675484 # Number of bytes of host memory used
|
||||
host_seconds 1146.75 # Real time elapsed on the host
|
||||
sim_insts 836933434 # Number of instructions simulated
|
||||
sim_ops 983519389 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -613,10 +613,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 283201595 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 283201595 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 283575709 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 283575709 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 283908330 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses
|
||||
|
|
@ -629,10 +629,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 6893121 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6893121 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8029572 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8029572 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9251082 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles
|
||||
|
|
@ -643,10 +643,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000
|
|||
system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 154677984000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 154677984000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 154677984000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 154677984000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -659,10 +659,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 290094716 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 290094716 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 291605281 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 291605281 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses
|
||||
|
|
@ -675,10 +675,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.023762 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.023762 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency
|
||||
|
|
@ -689,18 +689,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487
|
|||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22439.470307 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19263.540323 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 7313678 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits
|
||||
|
|
@ -725,10 +723,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778
|
|||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 6849886 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 6849886 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 7984572 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 7984572 # number of overall MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
|
||||
|
|
@ -747,16 +745,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 145533577500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 166975219500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217603000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217603000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417284500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417284500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -769,10 +765,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023613 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.023613 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027381 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.027381 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency
|
||||
|
|
@ -785,17 +781,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819
|
|||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 13331164 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks.
|
||||
|
|
@ -855,8 +848,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13331164 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses
|
||||
|
|
@ -895,7 +886,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188
|
|||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1036266 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks.
|
||||
|
|
@ -1087,8 +1077,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 879823 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses
|
||||
|
|
@ -1152,11 +1140,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014
|
|||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829950000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829950000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607551500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505276000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1210,12 +1196,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1372,11 +1355,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8860 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8900 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115564 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8860 # number of overall misses
|
||||
system.iocache.overall_misses::total 8900 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115524 # number of overall misses
|
||||
system.iocache.overall_misses::total 115564 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles
|
||||
|
|
@ -1385,11 +1368,11 @@ system.iocache.WriteReq_miss_latency::total 351000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1628892126 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1634313126 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1628892126 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1634313126 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1398,11 +1381,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8860 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8900 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8860 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8900 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -1424,19 +1407,17 @@ system.iocache.WriteReq_avg_miss_latency::total 117000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 183630.688315 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 183630.688315 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -1447,11 +1428,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8860 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8900 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8860 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8900 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -1460,11 +1441,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 201000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1185892126 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1189313126 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1185892126 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1189313126 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1486,12 +1467,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 67000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 76827 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 389416 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
|
|||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1764627 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2073818 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 91826344419 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 678044 # Number of bytes of host memory used
|
||||
host_seconds 556.61 # Real time elapsed on the host
|
||||
host_inst_rate 1129745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1327694 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 58788800163 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 676512 # Number of bytes of host memory used
|
||||
host_seconds 869.40 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -326,12 +326,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 4303548
|
|||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2275074 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280572 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 165146293 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 165037797 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 330184090 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 165355623 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 165252780 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 330608403 # number of overall hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 165290534 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 165229841 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 330520375 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 165499864 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 165444824 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 330944688 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 3016518 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::cpu1.data 2987065 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 6003583 # number of ReadReq misses
|
||||
|
|
@ -349,12 +349,12 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127060
|
|||
system.cpu0.dcache.LoadLockedReq_misses::total 253903 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 4311974 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 4259754 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 8571728 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 5100211 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 5057415 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 10157626 # number of overall misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 5073464 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 4745034 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 9818498 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 5861701 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 5542695 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 11404396 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88617297 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496846 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -373,12 +373,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 4557451
|
|||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275074 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2280573 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 169458267 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu1.data 169297551 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 170455834 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu1.data 170310195 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 340766029 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 170363998 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu1.data 169974875 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 171361565 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu1.data 170987519 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 342349084 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034040 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033753 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.033897 # miss rate for ReadReq accesses
|
||||
|
|
@ -396,23 +396,20 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055692
|
|||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055712 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025446 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025161 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.025304 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029921 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029695 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029780 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027916 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034207 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032416 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 8917390 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 8917390 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 14265253 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
|
||||
|
|
@ -473,11 +470,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 14265253 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 14265253 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -742,11 +736,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115517 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
|
||||
system.iocache.overall_misses::total 8853 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115477 # number of overall misses
|
||||
system.iocache.overall_misses::total 115517 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -755,11 +749,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -779,11 +773,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 1725796 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65319.576265 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 46978291 # Total number of references to valid blocks.
|
||||
|
|
@ -993,11 +984,8 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 1507081 # number of writebacks
|
||||
system.l2c.writebacks::total 1507081 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524934 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.799232 # Nu
|
|||
sim_ticks 51799232151500 # Number of ticks simulated
|
||||
final_tick 51799232151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1085172 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1275227 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 67259328222 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 678040 # Number of bytes of host memory used
|
||||
host_seconds 770.14 # Real time elapsed on the host
|
||||
host_inst_rate 780767 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 917508 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48392163425 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 677024 # Number of bytes of host memory used
|
||||
host_seconds 1070.41 # Real time elapsed on the host
|
||||
sim_insts 835736802 # Number of instructions simulated
|
||||
sim_ops 982105580 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -647,12 +647,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 3330034
|
|||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1801503 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1811825 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 3613328 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 141219995 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 141634455 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 282854450 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 141408447 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 141819876 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 283228323 # number of overall hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 141394196 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 141792419 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 283186615 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 141582648 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 141977840 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 283560488 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 2455322 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::cpu1.data 2424347 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 4879669 # number of ReadReq misses
|
||||
|
|
@ -671,12 +671,12 @@ system.cpu0.dcache.LoadLockedReq_misses::total 284928
|
|||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 3466251 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 3403542 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 6869793 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 4046045 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 3952170 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 7998215 # number of overall misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 4082188 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 4008411 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 8090599 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 4661982 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 4557039 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 9219021 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42484250000 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 41555213000 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::total 84039463000 # number of ReadReq miss cycles
|
||||
|
|
@ -692,12 +692,12 @@ system.cpu0.dcache.LoadLockedReq_miss_latency::total 4389496000
|
|||
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 80000 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 82000 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 76911781000 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu1.data 76394250500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 153306031500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 76911781000 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu1.data 76394250500 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 153306031500 # number of overall miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 101008852500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu1.data 100491798500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 201500651000 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 101008852500 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu1.data 100491798500 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 201500651000 # number of overall miss cycles
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 76020372 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 76099561 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 152119933 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -716,12 +716,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 3614962
|
|||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1801504 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1811826 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 3613330 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 144686246 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu1.data 145037997 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 289724243 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 145454492 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu1.data 145772046 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 291226538 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 145476384 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu1.data 145800830 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 291277214 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 146244630 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu1.data 146534879 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 292779509 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032298 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031858 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.032078 # miss rate for ReadReq accesses
|
||||
|
|
@ -740,12 +740,12 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078819
|
|||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.023957 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023467 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.023711 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027817 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027112 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.027464 # miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028061 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027492 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.027776 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031878 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.031099 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.031488 # miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17302.924016 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17140.785952 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17222.369591 # average ReadReq miss latency
|
||||
|
|
@ -761,20 +761,18 @@ system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15405.632300
|
|||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 80000 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22188.751190 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22445.514261 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 22315.960830 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19009.126443 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19329.697483 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 19167.530693 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24743.802221 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25070.233192 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 24905.529368 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21666.504182 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22051.994398 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 21857.055212 # average overall miss latency
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 7311510 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 7311510 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 10741 # number of ReadReq MSHR hits
|
||||
|
|
@ -810,12 +808,12 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::total 216981
|
|||
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3445673 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3381196 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::total 6826869 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4024602 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 3928918 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::total 7953520 # number of overall MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4061610 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3986065 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.demand_mshr_misses::total 8047675 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4640539 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4533787 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_misses::total 9174326 # number of overall MSHR misses
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17141 # number of ReadReq MSHR uncacheable
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16563 # number of ReadReq MSHR uncacheable
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33704 # number of ReadReq MSHR uncacheable
|
||||
|
|
@ -843,21 +841,18 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2986892000
|
|||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 79000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 81000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72358790500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 71851840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 144210630500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83070723000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 82359591500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 165430314500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95839925000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 95344519000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 191184444000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106551857500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 105852270500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 212404128000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3180599500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3018965000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199564500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3329040000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2888636500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217676500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6509639500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5907601500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12417241000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3180599500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3018965000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6199564500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032157 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031714 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031935 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -876,12 +871,12 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060023
|
|||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023815 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023312 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023563 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027669 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026952 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027310 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027919 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027339 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027629 # mshr miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031731 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.030940 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031335 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.940424 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15946.282062 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16033.164972 # average ReadReq mshr miss latency
|
||||
|
|
@ -900,22 +895,18 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13765.684553
|
|||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 79000 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20999.900600 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21250.421449 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21123.977990 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20640.729941 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20962.410389 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20799.635193 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23596.535610 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23919.459166 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23756.481717 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22961.095144 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23347.429092 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23152.014437 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185555.072633 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182271.629536 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183941.505459 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182713.501647 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 186495.997159 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184451.526299 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184090.933514 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184313.038188 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184196.534793 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89946.537145 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94189.598153 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91963.931289 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 13311280 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.820918 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 822940675 # Total number of references to valid blocks.
|
||||
|
|
@ -995,8 +986,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 13311280 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 13311280 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6677414 # number of ReadReq MSHR misses
|
||||
|
|
@ -1053,7 +1042,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043
|
|||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -1393,11 +1381,11 @@ system.iocache.WriteReq_misses::total 3 # nu
|
|||
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 8853 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 8893 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 115557 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 8853 # number of overall misses
|
||||
system.iocache.overall_misses::total 8893 # number of overall misses
|
||||
system.iocache.overall_misses::realview.ide 115517 # number of overall misses
|
||||
system.iocache.overall_misses::total 115557 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 1618419141 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 1623489641 # number of ReadReq miss cycles
|
||||
|
|
@ -1406,11 +1394,11 @@ system.iocache.WriteReq_miss_latency::total 351000 #
|
|||
system.iocache.WriteLineReq_miss_latency::realview.ide 13411968510 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 13411968510 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 1618419141 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 1623840641 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 15030387651 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 15035809151 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 1618419141 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 1623840641 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 15030387651 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 15035809151 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1419,11 +1407,11 @@ system.iocache.WriteReq_accesses::total 3 # nu
|
|||
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 8853 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 8893 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 8853 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 8893 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
|
|
@ -1445,19 +1433,17 @@ system.iocache.WriteReq_avg_miss_latency::total 117000
|
|||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125740.348290 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125740.348290 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 182810.249746 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 182597.620713 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 130114.075426 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 130115.952742 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 182810.249746 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 182597.620713 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 130114.075426 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 130115.952742 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 31642 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 9.436922 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||||
|
|
@ -1468,11 +1454,11 @@ system.iocache.WriteReq_mshr_misses::total 3 #
|
|||
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 8853 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 8893 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 8853 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 8893 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1175769141 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 1178989641 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -1481,11 +1467,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 201000
|
|||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073599158 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 8073599158 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 1175769141 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 1179190641 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 9249368299 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 9252789799 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 1175769141 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 1179190641 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 9249368299 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 9252789799 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1507,12 +1493,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 67000
|
|||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.884403 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.884403 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 132810.249746 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 132597.620713 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80069.325718 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 80071.218524 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 132810.249746 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 132597.620713 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80069.325718 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 80071.218524 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 1026360 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65258.201118 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 41749797 # Total number of references to valid blocks.
|
||||
|
|
@ -1807,8 +1792,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 872147 # number of writebacks
|
||||
system.l2c.writebacks::total 872147 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1170 # number of ReadReq MSHR misses
|
||||
|
|
@ -1911,14 +1894,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2965958000
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2811531000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 10675226000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3119505500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2710506500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 5830012000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2504816500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6085463500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2965958000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5522037500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 16505238000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2811531000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 10675226000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005479 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007656 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005703 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2006,15 +1986,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173032.961904
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169747.690636 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138947.871247 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171213.254665 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174995.577507 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172951.199976 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172095.345154 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83876.530641 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172283.710845 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 149317.320740 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87717.802321 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 96575.168720 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 76829 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 386652 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33709 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.230834 # Nu
|
|||
sim_ticks 5230834315000 # Number of ticks simulated
|
||||
final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 192642 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 380808 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2470040631 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 757076 # Number of bytes of host memory used
|
||||
host_seconds 2117.71 # Real time elapsed on the host
|
||||
host_inst_rate 185450 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 366593 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2377836678 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 757080 # Number of bytes of host memory used
|
||||
host_seconds 2199.83 # Real time elapsed on the host
|
||||
sim_insts 407959263 # Number of instructions simulated
|
||||
sim_ops 806441023 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -698,8 +698,6 @@ system.cpu.dcache.blocked::no_mshrs 52278 # nu
|
|||
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1592887 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits
|
||||
|
|
@ -738,10 +736,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2788550500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2788550500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -764,11 +760,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency
|
||||
system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks.
|
||||
|
|
@ -827,8 +820,6 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs 0
|
|||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses
|
||||
|
|
@ -855,7 +846,6 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.5
|
|||
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1273398 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks.
|
||||
|
|
@ -915,8 +905,6 @@ system.cpu.icache.blocked::no_mshrs 591 # nu
|
|||
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1273398 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits
|
||||
|
|
@ -949,7 +937,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks.
|
||||
|
|
@ -1013,8 +1000,6 @@ system.cpu.itb_walker_cache.blocked::no_mshrs 0
|
|||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses
|
||||
|
|
@ -1041,7 +1026,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.3
|
|||
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 108236 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks.
|
||||
|
|
@ -1202,8 +1186,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98548 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1266,10 +1248,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508
|
|||
system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2627781000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2627781000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93576407000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93576407000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -1314,11 +1294,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1491,26 +1468,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide 907
|
|||
system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 907 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses
|
||||
system.iocache.overall_misses::total 907 # number of overall misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
|
||||
system.iocache.overall_misses::total 47627 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 150838200 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 150838200 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 150838200 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 150838200 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1523,36 +1500,34 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397
|
|||
system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 166304.520397 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 166304.520397 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 105488200 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 105488200 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1565,11 +1540,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 573476 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 628544 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13974 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.140315 # Nu
|
|||
sim_ticks 5140314861500 # Number of ticks simulated
|
||||
final_tick 5140314861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 305571 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 607445 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6465827182 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 946272 # Number of bytes of host memory used
|
||||
host_seconds 795.00 # Real time elapsed on the host
|
||||
host_inst_rate 305956 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 608211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6473981728 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 946268 # Number of bytes of host memory used
|
||||
host_seconds 794.00 # Real time elapsed on the host
|
||||
sim_insts 242927760 # Number of instructions simulated
|
||||
sim_ops 482917054 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -526,8 +526,6 @@ system.cpu0.dcache.blocked::no_mshrs 19401 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.330550 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets 183 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 1556926 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 1556926 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 57 # number of ReadReq MSHR hits
|
||||
|
|
@ -584,12 +582,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total 20480553918
|
|||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30576787000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32909630500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63486417500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 482381000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 622576500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1104957500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31059168000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33532207000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64591375000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30576787000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 32909630500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 63486417500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.068076 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.074921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041660 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -623,13 +618,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21368.366823
|
|||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173837.429574 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170281.531671 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171975.808527 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 207475.698925 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 195655.719673 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200645.996005 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174276.268390 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170692.534411 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172397.215120 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171569.577708 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 167523.367507 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 169448.035050 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 963636 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 510.754232 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 132561753 # Total number of references to valid blocks.
|
||||
|
|
@ -723,8 +714,6 @@ system.cpu0.icache.blocked::no_mshrs 445 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.685393 # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 963636 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 963636 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 59693 # number of ReadReq MSHR hits
|
||||
|
|
@ -769,7 +758,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 13438.749848
|
|||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13025.550415 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13583.792891 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13438.749848 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.numCycles 2608018193 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
|
@ -1247,26 +1235,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide 902
|
|||
system.iocache.ReadReq_misses::total 902 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 902 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 902 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 902 # number of overall misses
|
||||
system.iocache.overall_misses::total 902 # number of overall misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47622 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47622 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47622 # number of overall misses
|
||||
system.iocache.overall_misses::total 47622 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126421308 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 126421308 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3306334979 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 3306334979 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 126421308 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 126421308 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 126421308 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 126421308 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 3432756287 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 3432756287 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 3432756287 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 3432756287 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 902 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 902 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 902 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 902 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 902 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 902 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47622 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47622 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47622 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47622 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1279,53 +1267,50 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 140156.660754
|
|||
system.iocache.ReadReq_avg_miss_latency::total 140156.660754 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70769.156229 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 70769.156229 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 140156.660754 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 140156.660754 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 140156.660754 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 140156.660754 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 72083.412855 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 72083.412855 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 72083.412855 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 72083.412855 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 26320 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 26320 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 739 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 739 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 739 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 27059 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 27059 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 27059 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 27059 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89471308 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 89471308 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1989257405 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 1989257405 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89471308 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 89471308 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89471308 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 89471308 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 2078728713 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 2078728713 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 2078728713 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 2078728713 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819290 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 0.819290 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.563356 # mshr miss rate for WriteLineReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::total 0.563356 # mshr miss rate for WriteLineReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819290 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 0.819290 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819290 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 0.819290 # mshr miss rate for overall accesses
|
||||
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.568204 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total 0.568204 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.568204 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total 0.568204 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::total 121070.782138 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75579.688640 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.688640 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 121070.782138 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 121070.782138 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76822.081858 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76822.081858 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76822.081858 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76822.081858 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 102044 # number of replacements
|
||||
system.l2c.tags.tagsinuse 64688.139772 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4947315 # Total number of references to valid blocks.
|
||||
|
|
@ -1602,8 +1587,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 93953 # number of writebacks
|
||||
system.l2c.writebacks::total 93953 # number of writebacks
|
||||
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 2 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1676,12 +1659,9 @@ system.l2c.overall_mshr_miss_latency::total 9728021512 #
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28378124000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30493776000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 58871900000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 455643500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 585976500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1041620000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28833767500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31079752500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 59913520000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28378124000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30493776000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 58871900000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000371 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.000267 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829091 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -1737,13 +1717,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 120088.652981
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161337.426731 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157781.379032 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159475.727261 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 195975.698925 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184153.519799 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189144.724896 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161789.311405 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158208.546282 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 159911.814790 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159232.647656 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 155225.688223 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 157131.685288 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 5063720 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5112994 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061235 # Nu
|
|||
sim_ticks 61234797500 # Number of ticks simulated
|
||||
final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 274685 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 276053 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 185648704 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 404860 # Number of bytes of host memory used
|
||||
host_seconds 329.84 # Real time elapsed on the host
|
||||
host_inst_rate 283902 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 285316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 191877896 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 404856 # Number of bytes of host memory used
|
||||
host_seconds 319.13 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -513,8 +513,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 943278 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits
|
||||
|
|
@ -565,7 +563,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
|
||||
|
|
@ -625,8 +622,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 5 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 5 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
|
||||
|
|
@ -653,7 +648,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
|
||||
|
|
@ -762,8 +756,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -822,7 +814,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.058199 # Nu
|
|||
sim_ticks 58199030500 # Number of ticks simulated
|
||||
final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 158181 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 158969 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101622775 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 491528 # Number of bytes of host memory used
|
||||
host_seconds 572.70 # Real time elapsed on the host
|
||||
host_inst_rate 149103 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 149846 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 95790656 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 491524 # Number of bytes of host memory used
|
||||
host_seconds 607.56 # Real time elapsed on the host
|
||||
sim_insts 90589799 # Number of instructions simulated
|
||||
sim_ops 91041030 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -786,8 +786,6 @@ system.cpu.dcache.blocked::no_mshrs 121409 # nu
|
|||
system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 5470634 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits
|
||||
|
|
@ -840,7 +838,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 447 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks.
|
||||
|
|
@ -900,8 +897,6 @@ system.cpu.icache.blocked::no_mshrs 219 # nu
|
|||
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 447 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 447 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits
|
||||
|
|
@ -934,7 +929,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1063,8 +1057,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 175 # number of writebacks
|
||||
|
|
@ -1148,7 +1140,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361598 # Nu
|
|||
sim_ticks 361597758500 # Number of ticks simulated
|
||||
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1193747 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1193796 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1770350920 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429888 # Number of bytes of host memory used
|
||||
host_seconds 204.25 # Real time elapsed on the host
|
||||
host_inst_rate 1238958 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1837400352 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 383872 # Number of bytes of host memory used
|
||||
host_seconds 196.80 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -172,8 +172,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 935266 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
|
||||
|
|
@ -216,7 +214,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
|
|
@ -276,8 +273,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 25 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 25 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
|
|
@ -304,7 +299,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
|
||||
|
|
@ -413,8 +407,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -463,7 +455,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.065987 # Nu
|
|||
sim_ticks 65986743500 # Number of ticks simulated
|
||||
final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 126294 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 222383 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52748930 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 126228 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 222267 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52721316 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 414760 # Number of bytes of host memory used
|
||||
host_seconds 1250.96 # Real time elapsed on the host
|
||||
host_seconds 1251.61 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -652,8 +652,6 @@ system.cpu.dcache.blocked::no_mshrs 43207 # nu
|
|||
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2066969 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits
|
||||
|
|
@ -696,7 +694,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 93 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks.
|
||||
|
|
@ -757,8 +754,6 @@ system.cpu.icache.blocked::no_mshrs 11 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 93 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 93 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits
|
||||
|
|
@ -791,7 +786,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 650 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks.
|
||||
|
|
@ -900,8 +894,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 280 # number of writebacks
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses
|
||||
|
|
@ -952,7 +944,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.366199 # Nu
|
|||
sim_ticks 366199170500 # Number of ticks simulated
|
||||
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 639917 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1126791 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1483253517 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 455604 # Number of bytes of host memory used
|
||||
host_seconds 246.89 # Real time elapsed on the host
|
||||
host_inst_rate 703769 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1239225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1631255376 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410416 # Number of bytes of host memory used
|
||||
host_seconds 224.49 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -170,8 +170,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2062482 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
|
||||
|
|
@ -206,7 +204,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
|
||||
|
|
@ -265,8 +262,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 24 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 24 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
|
|
@ -293,7 +288,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 313 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
|
||||
|
|
@ -402,8 +396,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 102 # number of writebacks
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
|
||||
|
|
@ -454,7 +446,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.412080 # Nu
|
|||
sim_ticks 412079966500 # Number of ticks simulated
|
||||
final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 374495 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 374495 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 252200387 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254932 # Number of bytes of host memory used
|
||||
host_seconds 1633.94 # Real time elapsed on the host
|
||||
host_inst_rate 367276 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 367276 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 247338871 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254928 # Number of bytes of host memory used
|
||||
host_seconds 1666.05 # Real time elapsed on the host
|
||||
sim_insts 611901617 # Number of instructions simulated
|
||||
sim_ops 611901617 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -446,8 +446,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2339413 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2339413 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143957 # number of ReadReq MSHR hits
|
||||
|
|
@ -490,7 +488,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3158 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks.
|
||||
|
|
@ -551,8 +548,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3158 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3158 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4986 # number of ReadReq MSHR misses
|
||||
|
|
@ -579,7 +574,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 347705 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks.
|
||||
|
|
@ -688,8 +682,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 293607 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293607 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses
|
||||
|
|
@ -744,7 +736,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5082776 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538426 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.362632 # Nu
|
|||
sim_ticks 362631828500 # Number of ticks simulated
|
||||
final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 285981 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 309756 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 204718125 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275016 # Number of bytes of host memory used
|
||||
host_seconds 1771.37 # Real time elapsed on the host
|
||||
host_inst_rate 263885 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 285822 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188900227 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275012 # Number of bytes of host memory used
|
||||
host_seconds 1919.70 # Real time elapsed on the host
|
||||
sim_insts 506579366 # Number of instructions simulated
|
||||
sim_ops 548692589 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -550,8 +550,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1069336 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits
|
||||
|
|
@ -602,7 +600,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 18130 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
|
||||
|
|
@ -663,8 +660,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 18130 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 18130 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses
|
||||
|
|
@ -691,7 +686,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 112376 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
|
||||
|
|
@ -800,8 +794,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 97210 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -862,7 +854,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.232865 # Nu
|
|||
sim_ticks 232864525000 # Number of ticks simulated
|
||||
final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 164421 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 178126 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75782118 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300244 # Number of bytes of host memory used
|
||||
host_seconds 3072.82 # Real time elapsed on the host
|
||||
host_inst_rate 163970 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 177638 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75574513 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300240 # Number of bytes of host memory used
|
||||
host_seconds 3081.26 # Real time elapsed on the host
|
||||
sim_insts 505234934 # Number of instructions simulated
|
||||
sim_ops 547348155 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -807,8 +807,6 @@ system.cpu.dcache.blocked::no_mshrs 5 # nu
|
|||
system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2817145 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits
|
||||
|
|
@ -861,7 +859,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 76528 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks.
|
||||
|
|
@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs 6762 # nu
|
|||
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 76528 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 76528 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits
|
||||
|
|
@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1087,8 +1081,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 292354 # number of writebacks
|
||||
|
|
@ -1172,7 +1164,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.708539 # Nu
|
|||
sim_ticks 708539449500 # Number of ticks simulated
|
||||
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 318121 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 344511 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 446353500 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303968 # Number of bytes of host memory used
|
||||
host_seconds 1587.40 # Real time elapsed on the host
|
||||
host_inst_rate 973862 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1054649 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1366418821 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273224 # Number of bytes of host memory used
|
||||
host_seconds 518.54 # Real time elapsed on the host
|
||||
sim_insts 504984064 # Number of instructions simulated
|
||||
sim_ops 546875315 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
|
||||
|
|
@ -346,7 +344,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
|
||||
|
|
@ -407,8 +404,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 9788 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 9788 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
||||
|
|
@ -435,7 +430,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 110394 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
|
||||
|
|
@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 96330 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
|
||||
|
|
@ -599,7 +591,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.481958 # Nu
|
|||
sim_ticks 481957625500 # Number of ticks simulated
|
||||
final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 104668 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 193689 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61009723 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318640 # Number of bytes of host memory used
|
||||
host_seconds 7899.69 # Real time elapsed on the host
|
||||
host_inst_rate 100765 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 186466 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 58734658 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318636 # Number of bytes of host memory used
|
||||
host_seconds 8205.68 # Real time elapsed on the host
|
||||
sim_insts 826847303 # Number of instructions simulated
|
||||
sim_ops 1530082520 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -665,8 +665,6 @@ system.cpu.dcache.blocked::no_mshrs 875 # nu
|
|||
system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2337968 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits
|
||||
|
|
@ -709,7 +707,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 4014 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks.
|
||||
|
|
@ -770,8 +767,6 @@ system.cpu.icache.blocked::no_mshrs 8 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 4014 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4014 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits
|
||||
|
|
@ -804,7 +799,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 355161 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks.
|
||||
|
|
@ -925,8 +919,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 294920 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses
|
||||
|
|
@ -989,7 +981,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.650501 # Nu
|
|||
sim_ticks 1650501252500 # Number of ticks simulated
|
||||
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 239314 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 442851 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 477703969 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314168 # Number of bytes of host memory used
|
||||
host_seconds 3455.07 # Real time elapsed on the host
|
||||
host_inst_rate 691787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1280153 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1380901785 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282548 # Number of bytes of host memory used
|
||||
host_seconds 1195.23 # Real time elapsed on the host
|
||||
sim_insts 826847304 # Number of instructions simulated
|
||||
sim_ops 1530082521 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2325221 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
|
||||
|
|
@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
|
||||
|
|
@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1253 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
|
||||
|
|
@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 348438 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
|
||||
|
|
@ -404,8 +398,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293208 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
|
||||
|
|
@ -460,7 +452,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.223533 # Nu
|
|||
sim_ticks 223532962500 # Number of ticks simulated
|
||||
final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 354404 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 354404 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 198715635 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258580 # Number of bytes of host memory used
|
||||
host_seconds 1124.89 # Real time elapsed on the host
|
||||
host_inst_rate 349202 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 349202 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 195799110 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258576 # Number of bytes of host memory used
|
||||
host_seconds 1141.64 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -415,8 +415,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits
|
||||
|
|
@ -459,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3190 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks.
|
||||
|
|
@ -519,8 +516,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3190 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3190 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5168 # number of ReadReq MSHR misses
|
||||
|
|
@ -547,7 +542,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks.
|
||||
|
|
@ -655,8 +649,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3892 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -705,7 +697,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.064189 # Nu
|
|||
sim_ticks 64188759000 # Number of ticks simulated
|
||||
final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 286389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 286389 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48946118 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 306108 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 306108 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52316361 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260628 # Number of bytes of host memory used
|
||||
host_seconds 1311.42 # Real time elapsed on the host
|
||||
host_seconds 1226.93 # Real time elapsed on the host
|
||||
sim_insts 375574794 # Number of instructions simulated
|
||||
sim_ops 375574794 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -666,8 +666,6 @@ system.cpu.dcache.blocked::no_mshrs 740 # nu
|
|||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.367568 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 655 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 655 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 838 # number of ReadReq MSHR hits
|
||||
|
|
@ -710,7 +708,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2132 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks.
|
||||
|
|
@ -770,8 +767,6 @@ system.cpu.icache.blocked::no_mshrs 8 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2132 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2132 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1585 # number of ReadReq MSHR hits
|
||||
|
|
@ -804,7 +799,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks.
|
||||
|
|
@ -912,8 +906,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -962,7 +954,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 11144 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2908 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567385 # Nu
|
|||
sim_ticks 567385356500 # Number of ticks simulated
|
||||
final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1390819 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1390819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1979434182 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 302276 # Number of bytes of host memory used
|
||||
host_seconds 286.64 # Real time elapsed on the host
|
||||
host_inst_rate 1272231 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1272231 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1810657439 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257040 # Number of bytes of host memory used
|
||||
host_seconds 313.36 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -193,8 +193,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
||||
|
|
@ -229,7 +227,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
|
|
@ -290,8 +287,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1769 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1769 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
|
||||
|
|
@ -318,7 +313,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks.
|
||||
|
|
@ -427,8 +421,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -477,7 +469,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.211715 # Nu
|
|||
sim_ticks 211714953000 # Number of ticks simulated
|
||||
final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 192926 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 231629 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 149595583 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280180 # Number of bytes of host memory used
|
||||
host_seconds 1415.25 # Real time elapsed on the host
|
||||
host_inst_rate 196459 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 235871 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 152335465 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280176 # Number of bytes of host memory used
|
||||
host_seconds 1389.79 # Real time elapsed on the host
|
||||
sim_insts 273037857 # Number of instructions simulated
|
||||
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -515,8 +515,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1010 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits
|
||||
|
|
@ -567,7 +565,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 38168 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks.
|
||||
|
|
@ -628,8 +625,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 38168 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 38168 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses
|
||||
|
|
@ -656,7 +651,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks.
|
||||
|
|
@ -765,8 +759,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 42 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -825,7 +817,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.111754 # Nu
|
|||
sim_ticks 111753553500 # Number of ticks simulated
|
||||
final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 152363 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 182928 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62361670 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292096 # Number of bytes of host memory used
|
||||
host_seconds 1792.02 # Real time elapsed on the host
|
||||
host_inst_rate 153930 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 184810 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63003104 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292088 # Number of bytes of host memory used
|
||||
host_seconds 1773.78 # Real time elapsed on the host
|
||||
sim_insts 273037220 # Number of instructions simulated
|
||||
sim_ops 327811602 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -771,8 +771,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1542955 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits
|
||||
|
|
@ -825,7 +823,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 726201 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks.
|
||||
|
|
@ -886,8 +883,6 @@ system.cpu.icache.blocked::no_mshrs 3051 # nu
|
|||
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 726201 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 726201 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits
|
||||
|
|
@ -920,7 +915,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1052,8 +1046,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1134,7 +1126,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.517291 # Nu
|
|||
sim_ticks 517291025500 # Number of ticks simulated
|
||||
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 222408 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 267009 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 421830266 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307072 # Number of bytes of host memory used
|
||||
host_seconds 1226.30 # Real time elapsed on the host
|
||||
host_inst_rate 647052 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 776811 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1227232141 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277364 # Number of bytes of host memory used
|
||||
host_seconds 421.51 # Real time elapsed on the host
|
||||
sim_insts 272739286 # Number of instructions simulated
|
||||
sim_ops 327433744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -295,8 +295,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 998 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
|
|
@ -345,7 +343,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
|
||||
|
|
@ -406,8 +403,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13796 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
|
||||
|
|
@ -434,7 +429,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
|
||||
|
|
@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -593,7 +585,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.504258 # Nu
|
|||
sim_ticks 504258263000 # Number of ticks simulated
|
||||
final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 397765 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 397765 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 215954385 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262596 # Number of bytes of host memory used
|
||||
host_seconds 2335.02 # Real time elapsed on the host
|
||||
host_inst_rate 386643 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 386643 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 209915985 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262852 # Number of bytes of host memory used
|
||||
host_seconds 2402.19 # Real time elapsed on the host
|
||||
sim_insts 928789150 # Number of instructions simulated
|
||||
sim_ops 928789150 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -443,8 +443,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88489 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits
|
||||
|
|
@ -487,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10567 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks.
|
||||
|
|
@ -548,8 +545,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 10567 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 10567 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses
|
||||
|
|
@ -576,7 +571,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 259940 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks.
|
||||
|
|
@ -685,8 +679,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
|
|
@ -741,7 +733,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.174766 # Nu
|
|||
sim_ticks 174766258500 # Number of ticks simulated
|
||||
final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 293073 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 293073 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 60802944 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 294264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 294264 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61050004 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263360 # Number of bytes of host memory used
|
||||
host_seconds 2874.31 # Real time elapsed on the host
|
||||
host_seconds 2862.67 # Real time elapsed on the host
|
||||
sim_insts 842382029 # Number of instructions simulated
|
||||
sim_ops 842382029 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -692,8 +692,6 @@ system.cpu.dcache.blocked::no_mshrs 347 # nu
|
|||
system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88604 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits
|
||||
|
|
@ -736,7 +734,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 4617 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks.
|
||||
|
|
@ -797,8 +794,6 @@ system.cpu.icache.blocked::no_mshrs 12 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 61.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 4617 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4617 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1927 # number of ReadReq MSHR hits
|
||||
|
|
@ -831,7 +826,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 259794 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks.
|
||||
|
|
@ -940,8 +934,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66682 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66682 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
|
|
@ -996,7 +988,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1568372 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781285 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.288319 # Nu
|
|||
sim_ticks 1288319411500 # Number of ticks simulated
|
||||
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1465054 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1465054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2032611527 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306300 # Number of bytes of host memory used
|
||||
host_seconds 633.82 # Real time elapsed on the host
|
||||
host_inst_rate 1388114 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1388114 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1925865262 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260804 # Number of bytes of host memory used
|
||||
host_seconds 668.96 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,8 +200,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88866 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
|
|
@ -236,7 +234,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 4618 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
|
||||
|
|
@ -296,8 +293,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 4618 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4618 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
|
||||
|
|
@ -324,7 +319,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 258847 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks.
|
||||
|
|
@ -433,8 +427,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
|
|
@ -489,7 +481,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.489946 # Nu
|
|||
sim_ticks 489945697500 # Number of ticks simulated
|
||||
final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 199747 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 245915 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 152758149 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280032 # Number of bytes of host memory used
|
||||
host_seconds 3207.33 # Real time elapsed on the host
|
||||
host_inst_rate 235921 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 290449 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 180421993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280028 # Number of bytes of host memory used
|
||||
host_seconds 2715.55 # Real time elapsed on the host
|
||||
sim_insts 640655085 # Number of instructions simulated
|
||||
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -537,8 +537,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88712 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits
|
||||
|
|
@ -589,7 +587,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 24859 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
|
||||
|
|
@ -648,8 +645,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 24859 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 24859 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses
|
||||
|
|
@ -676,7 +671,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 258808 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
|
||||
|
|
@ -785,8 +779,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -847,7 +839,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.326731 # Nu
|
|||
sim_ticks 326731324000 # Number of ticks simulated
|
||||
final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 133673 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164569 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68173047 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277340 # Number of bytes of host memory used
|
||||
host_seconds 4792.68 # Real time elapsed on the host
|
||||
host_inst_rate 138534 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 170554 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 70652444 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277336 # Number of bytes of host memory used
|
||||
host_seconds 4624.49 # Real time elapsed on the host
|
||||
sim_insts 640649299 # Number of instructions simulated
|
||||
sim_ops 788724958 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -811,8 +811,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2756452 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits
|
||||
|
|
@ -865,7 +863,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1979880 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
|
||||
|
|
@ -925,8 +922,6 @@ system.cpu.icache.blocked::no_mshrs 2912 # nu
|
|||
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1979880 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits
|
||||
|
|
@ -959,7 +954,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1084,8 +1078,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66334 # number of writebacks
|
||||
|
|
@ -1169,7 +1161,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.045756 # Nu
|
|||
sim_ticks 1045756396500 # Number of ticks simulated
|
||||
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 725560 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 891395 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1186735876 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325196 # Number of bytes of host memory used
|
||||
host_seconds 881.20 # Real time elapsed on the host
|
||||
host_inst_rate 744148 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 914231 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1217137628 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277972 # Number of bytes of host memory used
|
||||
host_seconds 859.19 # Real time elapsed on the host
|
||||
sim_insts 639366787 # Number of instructions simulated
|
||||
sim_ops 785501035 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88995 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
|
|
@ -352,7 +350,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
|
||||
|
|
@ -411,8 +408,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 8769 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 8769 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
|
||||
|
|
@ -439,7 +434,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 257772 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
|
||||
|
|
@ -548,8 +542,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
|
||||
|
|
@ -600,7 +592,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.059447 # Nu
|
|||
sim_ticks 59447065000 # Number of ticks simulated
|
||||
final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 412945 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 412945 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 277576735 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261724 # Number of bytes of host memory used
|
||||
host_seconds 214.16 # Real time elapsed on the host
|
||||
host_inst_rate 371878 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 371878 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 249972170 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261720 # Number of bytes of host memory used
|
||||
host_seconds 237.81 # Real time elapsed on the host
|
||||
sim_insts 88438073 # Number of instructions simulated
|
||||
sim_ops 88438073 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -442,8 +442,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168424 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168424 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits
|
||||
|
|
@ -486,7 +484,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 152872 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks.
|
||||
|
|
@ -547,8 +544,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 152872 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 152872 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154921 # number of ReadReq MSHR misses
|
||||
|
|
@ -575,7 +570,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 133382 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks.
|
||||
|
|
@ -684,8 +678,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 114469 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 114469 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses
|
||||
|
|
@ -740,7 +732,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 713421 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 353638 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.022275 # Nu
|
|||
sim_ticks 22275010500 # Number of ticks simulated
|
||||
final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 279038 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 279038 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 78093188 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 259704 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 259704 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72682241 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263768 # Number of bytes of host memory used
|
||||
host_seconds 285.24 # Real time elapsed on the host
|
||||
host_seconds 306.47 # Real time elapsed on the host
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_ops 79591756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -694,8 +694,6 @@ system.cpu.dcache.blocked::no_mshrs 89218 # nu
|
|||
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168806 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits
|
||||
|
|
@ -738,7 +736,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 90292 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks.
|
||||
|
|
@ -799,8 +796,6 @@ system.cpu.icache.blocked::no_mshrs 12 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 47.750000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 90292 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 90292 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12531 # number of ReadReq MSHR hits
|
||||
|
|
@ -833,7 +828,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 133082 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks.
|
||||
|
|
@ -942,8 +936,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 114419 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 114419 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses
|
||||
|
|
@ -998,7 +990,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.056803 # Nu
|
|||
sim_ticks 56802974500 # Number of ticks simulated
|
||||
final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 208655 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 266840 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 167132713 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280072 # Number of bytes of host memory used
|
||||
host_seconds 339.87 # Real time elapsed on the host
|
||||
host_inst_rate 222036 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 283951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177850276 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280068 # Number of bytes of host memory used
|
||||
host_seconds 319.39 # Real time elapsed on the host
|
||||
sim_insts 70915150 # Number of instructions simulated
|
||||
sim_ops 90690106 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -542,8 +542,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128389 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits
|
||||
|
|
@ -594,7 +592,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 43497 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
|
||||
|
|
@ -654,8 +651,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 43497 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 43497 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses
|
||||
|
|
@ -682,7 +677,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 96391 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
|
||||
|
|
@ -791,8 +785,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 86215 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -857,7 +849,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.033525 # Nu
|
|||
sim_ticks 33524756000 # Number of ticks simulated
|
||||
final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 145211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 185708 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68655135 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282260 # Number of bytes of host memory used
|
||||
host_seconds 488.31 # Real time elapsed on the host
|
||||
host_inst_rate 160372 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 205097 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75822829 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282256 # Number of bytes of host memory used
|
||||
host_seconds 442.15 # Real time elapsed on the host
|
||||
sim_insts 70907652 # Number of instructions simulated
|
||||
sim_ops 90682607 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -796,8 +796,6 @@ system.cpu.dcache.blocked::no_mshrs 6 # nu
|
|||
system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 486293 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits
|
||||
|
|
@ -850,7 +848,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 325000 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks.
|
||||
|
|
@ -911,8 +908,6 @@ system.cpu.icache.blocked::no_mshrs 16495 # nu
|
|||
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 325000 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 325000 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits
|
||||
|
|
@ -945,7 +940,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1070,8 +1064,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 97140 # number of writebacks
|
||||
|
|
@ -1155,7 +1147,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.208778 # Nu
|
|||
sim_ticks 1208777694500 # Number of ticks simulated
|
||||
final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 395749 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 395749 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 261924296 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 390102 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 390102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 258186532 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253640 # Number of bytes of host memory used
|
||||
host_seconds 4614.99 # Real time elapsed on the host
|
||||
host_seconds 4681.80 # Real time elapsed on the host
|
||||
sim_insts 1826378509 # Number of instructions simulated
|
||||
sim_ops 1826378509 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -457,8 +457,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3686603 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits
|
||||
|
|
@ -501,7 +499,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks.
|
||||
|
|
@ -559,8 +556,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses
|
||||
|
|
@ -587,7 +582,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1920891 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks.
|
||||
|
|
@ -692,8 +686,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022139 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
|
||||
|
|
@ -748,7 +740,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.669588 # Nu
|
|||
sim_ticks 669587683000 # Number of ticks simulated
|
||||
final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 206275 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 206275 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 79559671 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 207572 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 207572 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 80060022 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254664 # Number of bytes of host memory used
|
||||
host_seconds 8416.17 # Real time elapsed on the host
|
||||
host_seconds 8363.57 # Real time elapsed on the host
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_ops 1736043781 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -730,8 +730,6 @@ system.cpu.dcache.blocked::no_mshrs 1104455 # nu
|
|||
system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3727750 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits
|
||||
|
|
@ -782,7 +780,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks.
|
||||
|
|
@ -841,8 +838,6 @@ system.cpu.icache.blocked::no_mshrs 4 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits
|
||||
|
|
@ -875,7 +870,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1929018 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks.
|
||||
|
|
@ -980,8 +974,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1024304 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses
|
||||
|
|
@ -1036,7 +1028,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.636720 # Nu
|
|||
sim_ticks 2636719559500 # Number of ticks simulated
|
||||
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1488641 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1488641 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2156924734 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297352 # Number of bytes of host memory used
|
||||
host_seconds 1222.44 # Real time elapsed on the host
|
||||
host_inst_rate 1392133 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1392132 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2017091448 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252104 # Number of bytes of host memory used
|
||||
host_seconds 1307.19 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,8 +200,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3679426 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
|
||||
|
|
@ -236,7 +234,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
|
|
@ -295,8 +292,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
|
||||
|
|
@ -323,7 +318,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919525 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks.
|
||||
|
|
@ -428,8 +422,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021962 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
|
||||
|
|
@ -484,7 +476,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.116866 # Nu
|
|||
sim_ticks 1116865668500 # Number of ticks simulated
|
||||
final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 315195 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 339575 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 227915704 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272300 # Number of bytes of host memory used
|
||||
host_seconds 4900.35 # Real time elapsed on the host
|
||||
host_inst_rate 304077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 327597 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 219876370 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272296 # Number of bytes of host memory used
|
||||
host_seconds 5079.52 # Real time elapsed on the host
|
||||
sim_insts 1544563088 # Number of instructions simulated
|
||||
sim_ops 1664032481 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -548,8 +548,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3684567 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits
|
||||
|
|
@ -600,7 +598,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 29 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks.
|
||||
|
|
@ -659,8 +656,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 29 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 29 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses
|
||||
|
|
@ -687,7 +682,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 2013919 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks.
|
||||
|
|
@ -796,8 +790,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1050123 # number of writebacks
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -858,7 +850,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.767804 # Nu
|
|||
sim_ticks 767803843500 # Number of ticks simulated
|
||||
final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 188017 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 202560 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 93463451 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313392 # Number of bytes of host memory used
|
||||
host_seconds 8215.02 # Real time elapsed on the host
|
||||
host_inst_rate 224780 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 242166 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 111738196 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312364 # Number of bytes of host memory used
|
||||
host_seconds 6871.45 # Real time elapsed on the host
|
||||
sim_insts 1544563024 # Number of instructions simulated
|
||||
sim_ops 1664032416 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -809,8 +809,6 @@ system.cpu.dcache.blocked::no_mshrs 943594 # nu
|
|||
system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 17003710 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits
|
||||
|
|
@ -863,7 +861,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 589 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks.
|
||||
|
|
@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs 183 # nu
|
|||
system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 589 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 589 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits
|
||||
|
|
@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1086,8 +1080,6 @@ system.cpu.l2cache.blocked::no_mshrs 1 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1635896 # number of writebacks
|
||||
|
|
@ -1171,7 +1163,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu
|
|||
sim_ticks 2377029670500 # Number of ticks simulated
|
||||
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 872363 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 940093 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1347600333 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317216 # Number of bytes of host memory used
|
||||
host_seconds 1763.90 # Real time elapsed on the host
|
||||
host_inst_rate 1034140 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1114431 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1597508455 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269992 # Number of bytes of host memory used
|
||||
host_seconds 1487.96 # Real time elapsed on the host
|
||||
sim_insts 1538759602 # Number of instructions simulated
|
||||
sim_ops 1658228915 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -300,8 +300,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3681379 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
|
||||
|
|
@ -344,7 +342,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
|
||||
|
|
@ -403,8 +400,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 7 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
|
||||
|
|
@ -431,7 +426,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919027 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
|
||||
|
|
@ -540,8 +534,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
|
||||
|
|
@ -596,7 +588,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.895948 # Nu
|
|||
sim_ticks 5895947852500 # Number of ticks simulated
|
||||
final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 730138 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1137621 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1431096811 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317400 # Number of bytes of host memory used
|
||||
host_seconds 4119.88 # Real time elapsed on the host
|
||||
host_inst_rate 781389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1217475 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1531550481 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272448 # Number of bytes of host memory used
|
||||
host_seconds 3849.66 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3682716 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
|
||||
|
|
@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
|
||||
|
|
@ -265,8 +262,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 10 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 10 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
|
||||
|
|
@ -293,7 +288,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919169 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
|
||||
|
|
@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
|
||||
|
|
@ -454,7 +446,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.051906 # Nu
|
|||
sim_ticks 51905634500 # Number of ticks simulated
|
||||
final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 327219 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 327219 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 184808729 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257300 # Number of bytes of host memory used
|
||||
host_seconds 280.86 # Real time elapsed on the host
|
||||
host_inst_rate 330127 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 330127 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 186451175 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257296 # Number of bytes of host memory used
|
||||
host_seconds 278.39 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -415,8 +415,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
|
||||
|
|
@ -459,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13853 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks.
|
||||
|
|
@ -520,8 +517,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13853 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13853 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses
|
||||
|
|
@ -548,7 +543,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks.
|
||||
|
|
@ -657,8 +651,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -707,7 +699,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.021909 # Nu
|
|||
sim_ticks 21909208500 # Number of ticks simulated
|
||||
final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 236201 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 236201 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61475451 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258056 # Number of bytes of host memory used
|
||||
host_seconds 356.39 # Real time elapsed on the host
|
||||
host_inst_rate 220296 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 220296 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57335863 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258312 # Number of bytes of host memory used
|
||||
host_seconds 382.12 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -672,8 +672,6 @@ system.cpu.dcache.blocked::no_mshrs 392 # nu
|
|||
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 108 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 108 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 559 # number of ReadReq MSHR hits
|
||||
|
|
@ -724,7 +722,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 9515 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks.
|
||||
|
|
@ -785,8 +782,6 @@ system.cpu.icache.blocked::no_mshrs 4 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 9515 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 9515 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2951 # number of ReadReq MSHR hits
|
||||
|
|
@ -819,7 +814,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks.
|
||||
|
|
@ -928,8 +922,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -978,7 +970,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.130383 # Nu
|
|||
sim_ticks 130382890500 # Number of ticks simulated
|
||||
final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 248644 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 262111 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188134778 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275596 # Number of bytes of host memory used
|
||||
host_seconds 693.03 # Real time elapsed on the host
|
||||
host_inst_rate 248771 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 262245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188230845 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275588 # Number of bytes of host memory used
|
||||
host_seconds 692.68 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -515,8 +515,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
|
||||
|
|
@ -567,7 +565,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2881 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
|
||||
|
|
@ -628,8 +625,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2881 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2881 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses
|
||||
|
|
@ -656,7 +651,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
|
||||
|
|
@ -765,8 +759,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -825,7 +817,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.084938 # Nu
|
|||
sim_ticks 84937723500 # Number of ticks simulated
|
||||
final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 146803 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154755 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72367413 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 152098 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 160337 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 74977715 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271624 # Number of bytes of host memory used
|
||||
host_seconds 1173.70 # Real time elapsed on the host
|
||||
host_seconds 1132.84 # Real time elapsed on the host
|
||||
sim_insts 172303022 # Number of instructions simulated
|
||||
sim_ops 181635954 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -772,8 +772,6 @@ system.cpu.dcache.blocked::no_mshrs 2 # nu
|
|||
system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 72581 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits
|
||||
|
|
@ -826,7 +824,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 53623 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks.
|
||||
|
|
@ -887,8 +884,6 @@ system.cpu.icache.blocked::no_mshrs 3246 # nu
|
|||
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 53623 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 53623 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits
|
||||
|
|
@ -921,7 +916,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1040,8 +1034,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1114,7 +1106,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.103324 # Nu
|
|||
sim_ticks 103324153500 # Number of ticks simulated
|
||||
final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72241 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 121082 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56516511 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307592 # Number of bytes of host memory used
|
||||
host_seconds 1828.21 # Real time elapsed on the host
|
||||
host_inst_rate 75581 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 126680 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59129521 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307596 # Number of bytes of host memory used
|
||||
host_seconds 1747.42 # Real time elapsed on the host
|
||||
sim_insts 132071192 # Number of instructions simulated
|
||||
sim_ops 221363384 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -632,8 +632,6 @@ system.cpu.dcache.blocked::no_mshrs 8 # nu
|
|||
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 18 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits
|
||||
|
|
@ -676,7 +674,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 6515 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks.
|
||||
|
|
@ -737,8 +734,6 @@ system.cpu.icache.blocked::no_mshrs 30 # nu
|
|||
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 6515 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 6515 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits
|
||||
|
|
@ -771,7 +766,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks.
|
||||
|
|
@ -888,8 +882,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses
|
||||
|
|
@ -946,7 +938,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu
|
|||
sim_ticks 1869357988000 # Number of ticks simulated
|
||||
final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1993950 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1993950 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57344769220 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 333724 # Number of bytes of host memory used
|
||||
host_seconds 32.60 # Real time elapsed on the host
|
||||
host_inst_rate 1670594 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48045239456 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332628 # Number of bytes of host memory used
|
||||
host_seconds 38.91 # Real time elapsed on the host
|
||||
sim_insts 64999904 # Number of instructions simulated
|
||||
sim_ops 64999904 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -301,11 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 633127 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 618292 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks.
|
||||
|
|
@ -352,11 +349,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 618292 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -589,11 +583,8 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 144536 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.icache.tags.replacements 380647 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks.
|
||||
|
|
@ -639,11 +630,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 380647 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -704,18 +692,18 @@ system.iocache.ReadReq_misses::tsunami.ide 179 #
|
|||
system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 179 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 179 # number of overall misses
|
||||
system.iocache.overall_misses::total 179 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses
|
||||
system.iocache.overall_misses::total 41731 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -730,11 +718,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 999922 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks.
|
||||
|
|
@ -875,11 +860,8 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 80923 # number of writebacks
|
||||
system.l2c.writebacks::total 80923 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948784 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
|
|||
sim_ticks 1829331993500 # Number of ticks simulated
|
||||
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1828258 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1828257 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55705727715 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 331420 # Number of bytes of host memory used
|
||||
host_seconds 32.84 # Real time elapsed on the host
|
||||
host_inst_rate 1840131 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56067507873 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 330836 # Number of bytes of host memory used
|
||||
host_seconds 32.63 # Real time elapsed on the host
|
||||
sim_insts 60038469 # Number of instructions simulated
|
||||
sim_ops 60038469 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -282,11 +282,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833475 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 919603 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
|
||||
|
|
@ -333,11 +330,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 919603 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919603 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992419 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks.
|
||||
|
|
@ -430,11 +424,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74359 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -532,18 +523,18 @@ system.iocache.ReadReq_misses::tsunami.ide 174 #
|
|||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 174 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
|
||||
system.iocache.overall_misses::total 174 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
|
||||
system.iocache.overall_misses::total 41726 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -558,11 +549,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948291 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.982593 # Nu
|
|||
sim_ticks 1982592736000 # Number of ticks simulated
|
||||
final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 753764 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 753764 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24497172234 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 320072 # Number of bytes of host memory used
|
||||
host_seconds 80.93 # Real time elapsed on the host
|
||||
host_inst_rate 1178528 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38301918928 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332884 # Number of bytes of host memory used
|
||||
host_seconds 51.76 # Real time elapsed on the host
|
||||
sim_insts 61003209 # Number of instructions simulated
|
||||
sim_ops 61003209 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -580,8 +580,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 672790 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses
|
||||
|
|
@ -616,10 +614,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500
|
|||
system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -646,11 +642,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305
|
|||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 686545 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks.
|
||||
|
|
@ -708,8 +701,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 686545 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses
|
||||
|
|
@ -736,7 +727,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971
|
|||
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -989,8 +979,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 119726 # number of writebacks
|
||||
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses
|
||||
|
|
@ -1025,10 +1013,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000
|
|||
system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1055,11 +1041,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826
|
|||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.tags.replacements 331529 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks.
|
||||
|
|
@ -1119,8 +1102,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 331529 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses
|
||||
|
|
@ -1147,7 +1128,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283
|
|||
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -1232,26 +1212,26 @@ system.iocache.ReadReq_misses::tsunami.ide 175 #
|
|||
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 175 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
|
||||
system.iocache.overall_misses::total 175 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
|
||||
system.iocache.overall_misses::total 41727 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1264,36 +1244,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857
|
|||
system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1306,11 +1284,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 342136 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks.
|
||||
|
|
@ -1501,8 +1478,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 79408 # number of writebacks
|
||||
system.l2c.writebacks::total 79408 # number of writebacks
|
||||
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
|
||||
|
|
@ -1575,12 +1550,9 @@ system.l2c.overall_mshr_miss_latency::total 47046710502 #
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478327000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 1501902500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327774501 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 3078742001 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806101501 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774543000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 4580644501 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478327000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 23575500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 1501902500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -1636,13 +1608,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 115267.622116
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 7201 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 292681 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14131 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu
|
|||
sim_ticks 1941275996000 # Number of ticks simulated
|
||||
final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1255554 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43383023327 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332188 # Number of bytes of host memory used
|
||||
host_seconds 44.75 # Real time elapsed on the host
|
||||
host_inst_rate 1048317 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36222399744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 330588 # Number of bytes of host memory used
|
||||
host_seconds 53.59 # Real time elapsed on the host
|
||||
sim_insts 56182685 # Number of instructions simulated
|
||||
sim_ops 56182685 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -560,8 +560,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 834944 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses
|
||||
|
|
@ -592,10 +590,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -618,11 +614,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 928931 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks.
|
||||
|
|
@ -682,8 +675,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 928931 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 928931 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses
|
||||
|
|
@ -710,7 +701,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 336393 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks.
|
||||
|
|
@ -831,8 +821,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74281 # number of writebacks
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
|
||||
|
|
@ -871,10 +859,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000
|
|||
system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -905,11 +891,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1040,26 +1023,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 #
|
|||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
||||
system.iocache.overall_misses::total 173 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
||||
system.iocache.overall_misses::total 41725 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1072,36 +1055,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624
|
|||
system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1114,11 +1095,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 292274 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9653 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1852974 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36130480826 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581484 # Number of bytes of host memory used
|
||||
host_seconds 77.05 # Real time elapsed on the host
|
||||
host_inst_rate 1211130 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23615387886 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581436 # Number of bytes of host memory used
|
||||
host_seconds 117.88 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682017 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1698998 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
|
||||
|
|
@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698998 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
|
||||
|
|
@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide 240 #
|
|||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 240 # number of overall misses
|
||||
system.iocache.overall_misses::total 240 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36464 # number of overall misses
|
||||
system.iocache.overall_misses::total 36464 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu
|
|||
sim_ticks 2802882879000 # Number of ticks simulated
|
||||
final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1272297 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1550275 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24287502010 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 596572 # Number of bytes of host memory used
|
||||
host_seconds 115.40 # Real time elapsed on the host
|
||||
host_inst_rate 1338296 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1630694 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25547394462 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 592020 # Number of bytes of host memory used
|
||||
host_seconds 109.71 # Real time elapsed on the host
|
||||
sim_insts 146828562 # Number of instructions simulated
|
||||
sim_ops 178908371 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -365,11 +365,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 693475 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 1109624 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks.
|
||||
|
|
@ -416,11 +413,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 1109624 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
||||
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -555,11 +549,8 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 193020 # number of writebacks
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -876,11 +867,8 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 191946 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.icache.tags.replacements 523401 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks.
|
||||
|
|
@ -926,11 +914,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 523401 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
||||
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1064,11 +1049,8 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 32706 # number of writebacks
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1178,18 +1160,18 @@ system.iocache.ReadReq_misses::realview.ide 252 #
|
|||
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
||||
system.iocache.overall_misses::total 252 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36476 # number of overall misses
|
||||
system.iocache.overall_misses::total 36476 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1204,11 +1186,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 107729 # number of replacements
|
||||
system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 243914 # Total number of references to valid blocks.
|
||||
|
|
@ -1384,11 +1363,8 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 96268 # number of writebacks
|
||||
system.l2c.writebacks::total 96268 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 43996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 75724 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 30846 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1173204 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1428188 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22875895912 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581200 # Number of bytes of host memory used
|
||||
host_seconds 121.69 # Real time elapsed on the host
|
||||
host_inst_rate 1225194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23889629831 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 578692 # Number of bytes of host memory used
|
||||
host_seconds 116.53 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682017 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1698998 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
|
||||
|
|
@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698998 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
|
||||
|
|
@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide 240 #
|
|||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 240 # number of overall misses
|
||||
system.iocache.overall_misses::total 240 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36464 # number of overall misses
|
||||
system.iocache.overall_misses::total 36464 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.871806 # Nu
|
|||
sim_ticks 2871806231000 # Number of ticks simulated
|
||||
final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 937604 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 614632 # Number of bytes of host memory used
|
||||
host_seconds 140.24 # Real time elapsed on the host
|
||||
host_inst_rate 717242 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 867543 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15665668571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 616200 # Number of bytes of host memory used
|
||||
host_seconds 183.32 # Real time elapsed on the host
|
||||
sim_insts 131483712 # Number of instructions simulated
|
||||
sim_ops 159036662 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -687,8 +687,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 733230 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits
|
||||
|
|
@ -739,10 +737,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000
|
|||
system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -775,11 +771,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260
|
|||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 1147026 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks.
|
||||
|
|
@ -838,8 +831,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 1147026 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses
|
||||
|
|
@ -878,7 +869,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509
|
|||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued
|
||||
system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified
|
||||
system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1080,8 +1070,6 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 231848 # number of writebacks
|
||||
|
|
@ -1160,11 +1148,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140
|
|||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1224,12 +1210,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920
|
|||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency
|
||||
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1629,8 +1612,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 148452 # number of writebacks
|
||||
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits
|
||||
|
|
@ -1679,10 +1660,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000
|
|||
system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1715,11 +1694,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355
|
|||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.tags.replacements 463484 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks.
|
||||
|
|
@ -1778,8 +1754,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 463484 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses
|
||||
|
|
@ -1818,7 +1792,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446
|
|||
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued
|
||||
system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified
|
||||
system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -2015,8 +1988,6 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 26072 # number of writebacks
|
||||
|
|
@ -2093,11 +2064,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043
|
|||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2157,12 +2126,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050
|
|||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency
|
||||
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -2333,26 +2299,26 @@ system.iocache.ReadReq_misses::realview.ide 255 #
|
|||
system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 255 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 255 # number of overall misses
|
||||
system.iocache.overall_misses::total 255 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36479 # number of overall misses
|
||||
system.iocache.overall_misses::total 36479 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -2365,36 +2331,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608
|
|||
system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36206 # number of writebacks
|
||||
system.iocache.writebacks::total 36206 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -2407,11 +2371,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 124374 # number of replacements
|
||||
system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 421293 # Total number of references to valid blocks.
|
||||
|
|
@ -2693,8 +2656,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 97172 # number of writebacks
|
||||
system.l2c.writebacks::total 97172 # number of writebacks
|
||||
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -2798,14 +2759,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -2885,15 +2843,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 44095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 214453 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 30922 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu
|
|||
sim_ticks 2909586837500 # Number of ticks simulated
|
||||
final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 929184 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24040663881 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581600 # Number of bytes of host memory used
|
||||
host_seconds 121.03 # Real time elapsed on the host
|
||||
host_inst_rate 812558 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 979692 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21023218607 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 578440 # Number of bytes of host memory used
|
||||
host_seconds 138.40 # Real time elapsed on the host
|
||||
sim_insts 112457033 # Number of instructions simulated
|
||||
sim_ops 135588117 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -651,8 +651,6 @@ system.cpu.dcache.blocked::no_mshrs 20 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 683846 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits
|
||||
|
|
@ -699,10 +697,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -733,11 +729,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.tags.replacements 1695721 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks.
|
||||
|
|
@ -797,8 +790,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1695721 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses
|
||||
|
|
@ -837,7 +828,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932
|
|||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 87565 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks.
|
||||
|
|
@ -1017,8 +1007,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 81185 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
|
||||
|
|
@ -1078,11 +1066,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500
|
|||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1132,12 +1118,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1305,26 +1288,26 @@ system.iocache.ReadReq_misses::realview.ide 228 #
|
|||
system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 228 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 228 # number of overall misses
|
||||
system.iocache.overall_misses::total 228 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36452 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36452 # number of overall misses
|
||||
system.iocache.overall_misses::total 36452 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1337,36 +1320,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737
|
|||
system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1379,11 +1360,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 70548 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1278958 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1556926 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24937950041 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 579412 # Number of bytes of host memory used
|
||||
host_seconds 111.63 # Real time elapsed on the host
|
||||
host_inst_rate 1181524 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1438316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23038118447 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 579724 # Number of bytes of host memory used
|
||||
host_seconds 120.84 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -391,11 +391,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 682241 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 1698998 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
|
||||
|
|
@ -457,11 +454,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 1698998 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -728,18 +722,18 @@ system.iocache.ReadReq_misses::realview.ide 240 #
|
|||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 240 # number of overall misses
|
||||
system.iocache.overall_misses::total 240 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36464 # number of overall misses
|
||||
system.iocache.overall_misses::total 36464 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -754,11 +748,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 109907 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks.
|
||||
|
|
@ -948,11 +939,8 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 101944 # number of writebacks
|
||||
system.l2c.writebacks::total 101944 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74196 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.909645 # Nu
|
|||
sim_ticks 2909644861500 # Number of ticks simulated
|
||||
final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 955579 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1152126 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24724694945 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 580436 # Number of bytes of host memory used
|
||||
host_seconds 117.68 # Real time elapsed on the host
|
||||
host_inst_rate 753896 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 908960 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 19506336140 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 580236 # Number of bytes of host memory used
|
||||
host_seconds 149.16 # Real time elapsed on the host
|
||||
sim_insts 112454211 # Number of instructions simulated
|
||||
sim_ops 135584166 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -721,8 +721,6 @@ system.cpu0.dcache.blocked::no_mshrs 22 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.727273 # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 683901 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 683901 # number of writebacks
|
||||
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 477 # number of ReadReq MSHR hits
|
||||
|
|
@ -789,12 +787,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000
|
|||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2495078000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594854500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089932500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5543496500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824550500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368047000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3048418500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3229696000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278114500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -838,13 +833,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065
|
|||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373 # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.tags.replacements 1695677 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks.
|
||||
|
|
@ -924,8 +915,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 1695677 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 1695677 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840174 # number of ReadReq MSHR misses
|
||||
|
|
@ -982,7 +971,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671
|
|||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -1315,26 +1303,26 @@ system.iocache.ReadReq_misses::realview.ide 228 #
|
|||
system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 228 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 228 # number of overall misses
|
||||
system.iocache.overall_misses::total 228 # number of overall misses
|
||||
system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 36452 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::realview.ide 36452 # number of overall misses
|
||||
system.iocache.overall_misses::total 36452 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 28181877 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 28181877 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 28181877 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 28181877 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::realview.ide 4577089020 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 4577089020 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::realview.ide 4577089020 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 4577089020 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1347,36 +1335,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684
|
|||
system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 123604.723684 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 123604.723684 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 125564.825524 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 125564.825524 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 16781877 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 16781877 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 16781877 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 16781877 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::realview.ide 2753072506 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 2753072506 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::realview.ide 2753072506 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 2753072506 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1389,11 +1375,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency
|
||||
system.l2c.tags.replacements 87562 # number of replacements
|
||||
system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks.
|
||||
|
|
@ -1651,8 +1636,6 @@ system.l2c.blocked::no_mshrs 0 # nu
|
|||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 81183 # number of writebacks
|
||||
system.l2c.writebacks::total 81183 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses
|
||||
|
|
@ -1741,14 +1724,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2860870000
|
|||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3027916000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 6918904000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2341022000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2431506500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 4772528500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5201892000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2860870000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459422500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 11691432500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3027916000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 6918904000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1822,15 +1802,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667
|
|||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227 # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529 # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728 # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669 # average overall mshr uncacheable latency
|
||||
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 70546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu
|
|||
sim_ticks 5112151729000 # Number of ticks simulated
|
||||
final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1266983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2593792 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32374197845 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659352 # Number of bytes of host memory used
|
||||
host_seconds 157.91 # Real time elapsed on the host
|
||||
host_inst_rate 1369712 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34999130987 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 614748 # Number of bytes of host memory used
|
||||
host_seconds 146.07 # Real time elapsed on the host
|
||||
sim_insts 200067055 # Number of instructions simulated
|
||||
sim_ops 409581065 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -174,11 +174,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535790 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks.
|
||||
|
|
@ -225,11 +222,8 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs 0
|
|||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 792340 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks.
|
||||
|
|
@ -277,11 +271,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 792340 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 792340 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks.
|
||||
|
|
@ -332,11 +323,8 @@ system.cpu.itb_walker_cache.blocked::no_mshrs 0
|
|||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 106202 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks.
|
||||
|
|
@ -457,11 +445,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98175 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -575,18 +560,18 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide 903
|
|||
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 903 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses
|
||||
system.iocache.overall_misses::total 903 # number of overall misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
|
||||
system.iocache.overall_misses::total 47623 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -601,11 +586,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
|||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903644 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.194946 # Nu
|
|||
sim_ticks 5194946000500 # Number of ticks simulated
|
||||
final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 842553 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1624008 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34079125299 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659848 # Number of bytes of host memory used
|
||||
host_seconds 152.44 # Real time elapsed on the host
|
||||
host_inst_rate 910377 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36822413305 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 616280 # Number of bytes of host memory used
|
||||
host_seconds 141.08 # Real time elapsed on the host
|
||||
sim_insts 128436892 # Number of instructions simulated
|
||||
sim_ops 247560077 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -451,8 +451,6 @@ system.cpu.dcache.blocked::no_mshrs 514 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.521401 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1540773 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits
|
||||
|
|
@ -491,10 +489,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467
|
|||
system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786349500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786349500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918434500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918434500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070257 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -517,11 +513,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks.
|
||||
|
|
@ -581,8 +574,6 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs 0
|
|||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2983 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2983 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8791 # number of ReadReq MSHR misses
|
||||
|
|
@ -609,7 +600,6 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.5
|
|||
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 790489 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.213579 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 144635934 # Total number of references to valid blocks.
|
||||
|
|
@ -669,8 +659,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 790489 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 790489 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791008 # number of ReadReq MSHR misses
|
||||
|
|
@ -697,7 +685,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.069456 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks.
|
||||
|
|
@ -761,8 +748,6 @@ system.cpu.itb_walker_cache.blocked::no_mshrs 0
|
|||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks
|
||||
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses
|
||||
|
|
@ -789,7 +774,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9561.8
|
|||
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 87287 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64590.438483 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4366272 # Total number of references to valid blocks.
|
||||
|
|
@ -950,8 +934,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 80702 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 80702 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
|
|
@ -1004,10 +986,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16768538500
|
|||
system.cpu.l2cache.overall_mshr_miss_latency::total 18328972000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302755000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302755000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626267500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626267500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90929022500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90929022500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -1052,11 +1032,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241 # average WriteReq mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1228,26 +1205,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide 842
|
|||
system.iocache.ReadReq_misses::total 842 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
|
||||
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 842 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses
|
||||
system.iocache.overall_misses::total 842 # number of overall misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47562 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses
|
||||
system.iocache.overall_misses::total 47562 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles
|
||||
system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 138525690 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 138525690 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 138525690 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 138525690 # number of overall miss cycles
|
||||
system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
|
||||
|
|
@ -1260,36 +1237,34 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853
|
|||
system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency
|
||||
system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 164519.821853 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 164519.821853 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
|
||||
system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses
|
||||
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 96425690 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 96425690 # number of overall MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
|
||||
|
|
@ -1302,11 +1277,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853
|
|||
system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency
|
||||
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
|
||||
system.membus.trans_dist::ReadReq 546346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 588523 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13920 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000037 # Nu
|
|||
sim_ticks 37494000 # Number of ticks simulated
|
||||
final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 257461 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 257361 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1504149892 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 141195 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 141164 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 825166364 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252900 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 6413 # Number of instructions simulated
|
||||
sim_ops 6413 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -412,8 +412,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
|
||||
|
|
@ -454,7 +452,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks.
|
||||
|
|
@ -512,8 +509,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -538,7 +533,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
|
|
@ -628,8 +622,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -678,7 +670,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 22019000 # Number of ticks simulated
|
||||
final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 66596 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 66584 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 229093695 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228860 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 140516 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 140486 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 484379589 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253664 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 6385 # Number of instructions simulated
|
||||
sim_ops 6385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -656,8 +656,6 @@ system.cpu.dcache.blocked::no_mshrs 43 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits
|
||||
|
|
@ -698,7 +696,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks.
|
||||
|
|
@ -756,8 +753,6 @@ system.cpu.icache.blocked::no_mshrs 1 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -788,7 +783,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
|
|
@ -878,8 +872,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -928,7 +920,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu
|
|||
sim_ticks 35682500 # Number of ticks simulated
|
||||
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 44587 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44581 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 248411942 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226904 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 421865 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 421312 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2345119890 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251096 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -190,8 +190,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
||||
|
|
@ -224,7 +222,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
|
||||
|
|
@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
|
|
@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -448,7 +440,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 20320000 # Number of ticks simulated
|
||||
final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31344 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31334 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 243267003 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230348 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 183657 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 183501 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1441333472 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251592 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2585 # Number of instructions simulated
|
||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -412,8 +412,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16 # number of WriteReq MSHR hits
|
||||
|
|
@ -454,7 +452,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 119.123012 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 750 # Total number of references to valid blocks.
|
||||
|
|
@ -512,8 +509,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 225 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -538,7 +533,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 147.162900 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
@ -622,8 +616,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -672,7 +664,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64103.225806
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63957.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64488.235294 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64103.225806 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 12409500 # Number of ticks simulated
|
||||
final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 12168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12166 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63007670 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231556 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_inst_rate 67215 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 67181 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 349098234 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252356 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -655,8 +655,6 @@ system.cpu.dcache.blocked::no_mshrs 6 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
|
||||
|
|
@ -697,7 +695,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks.
|
||||
|
|
@ -755,8 +752,6 @@ system.cpu.icache.blocked::no_mshrs 2 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -787,7 +782,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
@ -871,8 +865,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -921,7 +913,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu
|
|||
sim_ticks 18239500 # Number of ticks simulated
|
||||
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 29160 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29152 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 206272099 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229424 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 277034 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 276552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1954350939 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249792 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -190,8 +190,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
|
||||
|
|
@ -224,7 +222,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
|
|
@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
@ -392,8 +386,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -442,7 +434,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu
|
|||
sim_ticks 29977500 # Number of ticks simulated
|
||||
final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 167534 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 196036 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1088591965 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269228 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_inst_rate 89930 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 105235 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 584953104 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268772 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -504,8 +504,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits
|
||||
|
|
@ -546,7 +544,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
|
||||
|
|
@ -604,8 +601,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 4 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses
|
||||
|
|
@ -632,7 +627,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
|
||||
|
|
@ -730,8 +724,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -786,7 +778,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 17232500 # Number of ticks simulated
|
||||
final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 9367 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 10970 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35022410 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245324 # Number of bytes of host memory used
|
||||
host_seconds 0.49 # Real time elapsed on the host
|
||||
host_inst_rate 43939 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51450 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 164826819 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269540 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -878,8 +878,6 @@ system.cpu.dcache.blocked::no_mshrs 3 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits
|
||||
|
|
@ -922,7 +920,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks.
|
||||
|
|
@ -980,8 +977,6 @@ system.cpu.icache.blocked::no_mshrs 5 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits
|
||||
|
|
@ -1014,7 +1009,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
|
||||
|
|
@ -1112,8 +1106,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -1168,7 +1160,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
|
|||
sim_ticks 18821000 # Number of ticks simulated
|
||||
final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 9099 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 10656 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37131488 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241712 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_inst_rate 49791 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58299 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 203978556 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266084 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -759,8 +759,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
|
||||
|
|
@ -805,7 +803,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 44 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks.
|
||||
|
|
@ -863,8 +860,6 @@ system.cpu.icache.blocked::no_mshrs 95 # nu
|
|||
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 44 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 44 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits
|
||||
|
|
@ -897,7 +892,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
||||
|
|
@ -1007,8 +1001,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -1079,7 +1071,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 28298500 # Number of ticks simulated
|
||||
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 286813 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 333728 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1769783602 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267436 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 441317 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 514292 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2726097982 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267744 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4566 # Number of instructions simulated
|
||||
sim_ops 5330 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -284,8 +284,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
|
||||
|
|
@ -318,7 +316,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
|
||||
|
|
@ -376,8 +373,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
|
||||
|
|
@ -404,7 +399,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
|
|
@ -498,8 +492,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -548,7 +540,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu
|
|||
sim_ticks 22532000 # Number of ticks simulated
|
||||
final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 106399 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 106364 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 479269632 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251364 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 65525 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 65509 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 295199371 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251356 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 4999 # Number of instructions simulated
|
||||
sim_ops 4999 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -640,8 +640,6 @@ system.cpu.dcache.blocked::no_mshrs 10 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
|
||||
|
|
@ -682,7 +680,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
|
||||
|
|
@ -740,8 +737,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 17 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 17 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits
|
||||
|
|
@ -774,7 +769,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
|
||||
|
|
@ -868,8 +862,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -918,7 +910,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000034 # Nu
|
|||
sim_ticks 33932500 # Number of ticks simulated
|
||||
final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 42153 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42149 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 253513577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224784 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_inst_rate 442497 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 441783 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2653552582 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249064 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5641 # Number of instructions simulated
|
||||
sim_ops 5641 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -176,8 +176,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
|
||||
|
|
@ -210,7 +208,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
|
||||
|
|
@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
|
||||
|
|
@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
|
||||
|
|
@ -390,8 +384,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -440,7 +432,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 19908000 # Number of ticks simulated
|
||||
final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 56421 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56413 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 194020204 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225060 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 130311 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 130281 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 447700777 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249300 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -641,8 +641,6 @@ system.cpu.dcache.blocked::no_mshrs 6 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
|
||||
|
|
@ -683,7 +681,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks.
|
||||
|
|
@ -741,8 +738,6 @@ system.cpu.icache.blocked::no_mshrs 5 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -773,7 +768,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks.
|
||||
|
|
@ -867,8 +861,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -917,7 +909,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu
|
|||
sim_ticks 30526500 # Number of ticks simulated
|
||||
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 33063 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 33056 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 189395194 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228956 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 608531 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 607803 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3479427932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249516 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -158,8 +158,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
|
||||
|
|
@ -192,7 +190,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
|
|
@ -250,8 +247,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -276,7 +271,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
|
|
@ -370,8 +364,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -420,7 +412,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 21273500 # Number of ticks simulated
|
||||
final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 39176 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 70969 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 151562567 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245924 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 70008 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 126817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 276755373 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271684 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -625,8 +625,6 @@ system.cpu.dcache.blocked::no_mshrs 3 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -665,7 +663,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks.
|
||||
|
|
@ -723,8 +720,6 @@ system.cpu.icache.blocked::no_mshrs 3 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -755,7 +750,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
|
|
@ -845,8 +839,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -895,7 +887,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu
|
|||
sim_ticks 30886500 # Number of ticks simulated
|
||||
final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79759 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 144442 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 457524996 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247116 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 235920 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 427054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1352150005 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266824 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -161,8 +161,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
|
||||
|
|
@ -195,7 +193,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
|
||||
|
|
@ -253,8 +250,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -279,7 +274,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
|
|
@ -369,8 +363,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -419,7 +411,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu
|
|||
sim_ticks 25580500 # Number of ticks simulated
|
||||
final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 50796 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50792 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98611945 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229596 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 85448 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 85436 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 171120344 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253996 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 12770 # Number of instructions simulated
|
||||
sim_ops 12770 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -799,8 +799,6 @@ system.cpu.dcache.blocked::no_mshrs 130 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
|
||||
|
|
@ -841,7 +839,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements::0 7 # number of replacements
|
||||
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.icache.tags.replacements::total 7 # number of replacements
|
||||
|
|
@ -901,8 +898,6 @@ system.cpu.icache.blocked::no_mshrs 55 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 7 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits
|
||||
|
|
@ -935,7 +930,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
|
||||
|
|
@ -1031,8 +1025,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -1081,7 +1073,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000029 # Nu
|
|||
sim_ticks 28845500 # Number of ticks simulated
|
||||
final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 12271 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12271 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22902062 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227268 # Number of bytes of host memory used
|
||||
host_seconds 1.18 # Real time elapsed on the host
|
||||
host_inst_rate 68981 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 68975 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 137812851 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251992 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -621,8 +621,6 @@ system.cpu.dcache.blocked::no_mshrs 23 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
|
||||
|
|
@ -663,7 +661,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks.
|
||||
|
|
@ -721,8 +718,6 @@ system.cpu.icache.blocked::no_mshrs 2 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -753,7 +748,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
|
|
@ -843,8 +837,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -893,7 +885,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu
|
|||
sim_ticks 44282500 # Number of ticks simulated
|
||||
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17930 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17930 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52364992 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228848 # Number of bytes of host memory used
|
||||
host_seconds 0.85 # Real time elapsed on the host
|
||||
host_inst_rate 298703 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 298583 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 871748609 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249440 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -162,8 +162,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
|
||||
|
|
@ -196,7 +194,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
|
|
@ -254,8 +251,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -280,7 +275,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
|
|
@ -370,8 +364,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -420,7 +412,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000061 # Nu
|
|||
sim_ticks 61470000 # Number of ticks simulated
|
||||
final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 62593 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 62569 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 595804848 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 614668 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 583425 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 580281 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5518802940 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 637904 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6453 # Number of instructions simulated
|
||||
sim_ops 6453 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -409,8 +409,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
||||
|
|
@ -443,7 +441,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 62 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
|
||||
|
|
@ -501,8 +498,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -527,7 +522,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -647,8 +641,6 @@ system.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses
|
||||
|
|
@ -693,7 +685,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408
|
|||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
|
||||
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu
|
|||
sim_ticks 49855000 # Number of ticks simulated
|
||||
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 411650 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 475781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4107877451 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 655016 # Number of bytes of host memory used
|
||||
host_inst_rate 523400 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 604831 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5220928914 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 655332 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4988 # Number of instructions simulated
|
||||
sim_ops 5770 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -503,8 +503,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
|
||||
|
|
@ -537,7 +535,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 70 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks.
|
||||
|
|
@ -595,8 +592,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -621,7 +616,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321
|
|||
system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -744,8 +738,6 @@ system.l2cache.blocked::no_mshrs 0 # nu
|
|||
system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
|
||||
system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
||||
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses
|
||||
|
|
@ -790,7 +782,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114
|
|||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
|
||||
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadResp 308 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue