diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 0141fa2a0..4df13fb2b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -221,6 +221,7 @@ BaseCache::CacheEvent::process()
         }
         else if (!cachePort->isCpuSide)
         {
+            assert(cachePort->cache->doMasterRequest());
             //MSHR
             pkt = cachePort->cache->getPacket();
             MSHR* mshr = (MSHR*) pkt->senderState;
@@ -238,6 +239,7 @@ BaseCache::CacheEvent::process()
         }
         else
         {
+            assert(cachePort->cache->doSlaveRequest());
             //CSHR
             pkt = cachePort->cache->getCoherencePacket();
             bool success = cachePort->sendTiming(pkt);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 41c28f3a1..563b1ca8b 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -467,7 +467,7 @@ class BaseCache : public MemObject
      */
     void setMasterRequest(RequestCause cause, Tick time)
     {
-        if (!doMasterRequest() && memSidePort->drainList.empty())
+        if (!doMasterRequest() && !memSidePort->waitingOnRetry)
         {
             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
             reqCpu->schedule(time);