mem: Add DRAMPower wrapping class
This patch adds a class to wrap DRAMPower Library in gem5. This class initiates an object of class MemorySpecification of the DRAMPower Library, passes the parameters from DRAMCtrl.py to this object and creates an object of drampower library using the memory specification.
This commit is contained in:
Omar Naji
parent
00b37ffe50
commit
afc6ce6228
3 changed files with 265 additions and 0 deletions
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@ -48,6 +48,7 @@ Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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Source('addr_mapper.cc')
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Source('bridge.cc')
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Source('bridge.cc')
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Source('coherent_xbar.cc')
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Source('coherent_xbar.cc')
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Source('drampower.cc')
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Source('dram_ctrl.cc')
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Source('dram_ctrl.cc')
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Source('mem_object.cc')
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Source('mem_object.cc')
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Source('mport.cc')
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Source('mport.cc')
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161
src/mem/drampower.cc
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161
src/mem/drampower.cc
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/*
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* Copyright (const c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (const INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (const INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Omar Naji
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*/
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#include "base/intmath.hh"
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#include "mem/drampower.hh"
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#include "sim/core.hh"
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using namespace Data;
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DRAMPower::DRAMPower(const DRAMCtrlParams* p, bool include_io) :
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powerlib(libDRAMPower(getMemSpec(p), include_io))
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{
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}
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Data::MemArchitectureSpec
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DRAMPower::getArchParams(const DRAMCtrlParams* p)
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{
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Data::MemArchitectureSpec archSpec;
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archSpec.burstLength = p->burst_length;
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archSpec.nbrOfBanks = p->banks_per_rank;
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// One DRAMPower instance per rank, hence set this to 1
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archSpec.nbrOfRanks = 1;
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archSpec.dataRate = getDataRate(p);
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// For now we can ignore the number of columns and rows as they
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// are not used in the power calculation.
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archSpec.nbrOfColumns = 0;
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archSpec.nbrOfRows = 0;
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archSpec.width = p->device_bus_width;
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archSpec.nbrOfBankGroups = p->bank_groups_per_rank;
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archSpec.dll = p->dll;
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archSpec.twoVoltageDomains = hasTwoVDD(p);
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// Keep this disabled for now until the model is firmed up.
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archSpec.termination = false;
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return archSpec;
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}
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Data::MemTimingSpec
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DRAMPower::getTimingParams(const DRAMCtrlParams* p)
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{
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// Set the values that are used for power calculations and ignore
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// the ones only used by the controller functionality in DRAMPower
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// All DRAMPower timings are in clock cycles
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Data::MemTimingSpec timingSpec;
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timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
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timingSpec.RCD = divCeil(p->tRCD, p->tCK);
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timingSpec.RL = divCeil(p->tCL, p->tCK);
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timingSpec.RP = divCeil(p->tRP, p->tCK);
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timingSpec.RFC = divCeil(p->tRFC, p->tCK);
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timingSpec.RAS = divCeil(p->tRAS, p->tCK);
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// Write latency is read latency - 1 cycle
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// Source: B.Jacob Memory Systems Cache, DRAM, Disk
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timingSpec.WL = timingSpec.RL - 1;
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timingSpec.DQSCK = 0; // ignore for now
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timingSpec.RTP = divCeil(p->tRTP, p->tCK);
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timingSpec.WR = divCeil(p->tWR, p->tCK);
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timingSpec.XP = divCeil(p->tXP, p->tCK);
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timingSpec.XPDLL = divCeil(p->tXPDLL, p->tCK);
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timingSpec.XS = divCeil(p->tXS, p->tCK);
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timingSpec.XSDLL = divCeil(p->tXSDLL, p->tCK);
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// Clock period in ns
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timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
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assert(timingSpec.clkPeriod != 0);
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timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
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return timingSpec;
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}
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Data::MemPowerSpec
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DRAMPower::getPowerParams(const DRAMCtrlParams* p)
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{
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// All DRAMPower currents are in mA
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Data::MemPowerSpec powerSpec;
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powerSpec.idd0 = p->IDD0 * 1000;
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powerSpec.idd02 = p->IDD02 * 1000;
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powerSpec.idd2p0 = p->IDD2P0 * 1000;
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powerSpec.idd2p02 = p->IDD2P02 * 1000;
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powerSpec.idd2p1 = p->IDD2P1 * 1000;
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powerSpec.idd2p12 = p->IDD2P12 * 1000;
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powerSpec.idd2n = p->IDD2N * 1000;
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powerSpec.idd2n2 = p->IDD2N2 * 1000;
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powerSpec.idd3p0 = p->IDD3P0 * 1000;
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powerSpec.idd3p02 = p->IDD3P02 * 1000;
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powerSpec.idd3p1 = p->IDD3P1 * 1000;
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powerSpec.idd3p12 = p->IDD3P12 * 1000;
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powerSpec.idd3n = p->IDD3N * 1000;
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powerSpec.idd3n2 = p->IDD3N2 * 1000;
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powerSpec.idd4r = p->IDD4R * 1000;
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powerSpec.idd4r2 = p->IDD4R2 * 1000;
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powerSpec.idd4w = p->IDD4W * 1000;
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powerSpec.idd4w2 = p->IDD4W2 * 1000;
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powerSpec.idd5 = p->IDD5 * 1000;
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powerSpec.idd52 = p->IDD52 * 1000;
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powerSpec.idd6 = p->IDD6 * 1000;
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powerSpec.idd62 = p->IDD62 * 1000;
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powerSpec.vdd = p->VDD;
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powerSpec.vdd2 = p->VDD2;
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return powerSpec;
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}
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Data::MemorySpecification
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DRAMPower::getMemSpec(const DRAMCtrlParams* p)
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{
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Data::MemorySpecification memSpec;
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memSpec.memArchSpec = getArchParams(p);
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memSpec.memTimingSpec = getTimingParams(p);
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memSpec.memPowerSpec = getPowerParams(p);
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return memSpec;
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}
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bool
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DRAMPower::hasTwoVDD(const DRAMCtrlParams* p)
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{
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return p->VDD2 == 0 ? false : true;
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}
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uint8_t
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DRAMPower::getDataRate(const DRAMCtrlParams* p)
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{
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uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
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uint8_t data_rate = p->burst_length / burst_cycles;
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if (data_rate != 1 && data_rate != 2)
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fatal("Got unexpected data rate %d, should be 1 or 2\n");
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return data_rate;
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}
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103
src/mem/drampower.hh
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103
src/mem/drampower.hh
Normal file
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@ -0,0 +1,103 @@
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/*
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* Copyright (const c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be rued as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (const INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (const INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Omar Naji
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*/
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/**
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* @file
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* DRAMPower declaration
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*/
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#ifndef __MEM_DRAM_POWER_HH__
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#define __MEM_DRAM_POWER_HH__
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#include "libdrampower/LibDRAMPower.h"
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#include "params/DRAMCtrl.hh"
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/**
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* DRAMPower is a standalone tool which calculates the power consumed by a
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* DRAM in the system. This class wraps the DRAMPower library.
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*/
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class DRAMPower
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{
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private:
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/**
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* Transform the architechture parameters defined in
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* DRAMCtrlParams to the memSpec of DRAMPower
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*/
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static Data::MemArchitectureSpec getArchParams(const DRAMCtrlParams* p);
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/**
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* Transforms the timing parameters defined in DRAMCtrlParams to
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* the memSpec of DRAMPower
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*/
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static Data::MemTimingSpec getTimingParams(const DRAMCtrlParams* p);
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/**
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* Transforms the power and current parameters defined in
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* DRAMCtrlParam to the memSpec of DRAMPower
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*/
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static Data::MemPowerSpec getPowerParams(const DRAMCtrlParams* p);
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/**
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* Determine data rate, either one or two.
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*/
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static uint8_t getDataRate(const DRAMCtrlParams* p);
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/**
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* Determine if DRAM has two voltage domains (or one)
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*/
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static bool hasTwoVDD(const DRAMCtrlParams* p);
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/**
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* Return an instance of MemSpec based on the DRAMCtrlParams
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*/
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static Data::MemorySpecification getMemSpec(const DRAMCtrlParams* p);
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public:
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// Instance of DRAMPower Library
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libDRAMPower powerlib;
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DRAMPower(const DRAMCtrlParams* p, bool include_io);
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};
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#endif //__MEM_DRAM_POWER_HH__
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