sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

arm: add preliminary ISA splits for ARM arch

Browse source
This commit is contained in:
Curtis Dunham 2014-05-09 18:58:47 -04:00
parent fe27f937aa
commit af39ab297f
3 changed files with 26 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/arch/arm/isa/insts/insts.isa
View file

@ -53,6 +53,9 @@
##include "misc.isa" ##include "misc.isa"
##include "misc64.isa" ##include "misc64.isa"
split exec;
split decoder;
//Stores of a single item, AArch64 //Stores of a single item, AArch64
##include "str64.isa" ##include "str64.isa"
@ -65,6 +68,8 @@
//Load/store multiple //Load/store multiple
##include "macromem.isa" ##include "macromem.isa"
split exec;
//Data processing instructions //Data processing instructions
##include "data.isa" ##include "data.isa"
@ -85,12 +90,15 @@
##include "fp.isa" ##include "fp.isa"
##include "fp64.isa" ##include "fp64.isa"
split exec;
//Neon //Neon
##include "neon.isa" ##include "neon.isa"
//AArch64 Neon //AArch64 Neon
##include "neon64.isa" ##include "neon64.isa"
split decoder;
##include "neon64_mem.isa" ##include "neon64_mem.isa"
//m5 Psuedo-ops //m5 Pseudo-ops
##include "m5ops.isa" ##include "m5ops.isa"

22
src/arch/arm/isa/insts/neon.isa
View file

@ -1058,7 +1058,11 @@ output header {{
} }
}}; }};
output exec {{ let {{
header_output = ""
exec_output = ""
vcompares = '''
static float static float
vcgtFunc(float op1, float op2) vcgtFunc(float op1, float op2)
{ {
@ -1082,7 +1086,8 @@ output exec {{
return 2.0; return 2.0;
return (op1 == op2) ? 0.0 : 1.0; return (op1 == op2) ? 0.0 : 1.0;
} }
'''
vcomparesL = '''
static float static float
vcleFunc(float op1, float op2) vcleFunc(float op1, float op2)
{ {
@ -1098,7 +1103,8 @@ output exec {{
return 2.0; return 2.0;
return (op1 < op2) ? 0.0 : 1.0; return (op1 < op2) ? 0.0 : 1.0;
} }
'''
vacomparesG = '''
static float static float
vacgtFunc(float op1, float op2) vacgtFunc(float op1, float op2)
{ {
@ -1114,12 +1120,9 @@ output exec {{
return 2.0; return 2.0;
return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0; return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0;
} }
}}; '''
let {{ exec_output += vcompares + vacomparesG
header_output = ""
exec_output = ""
smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t") smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t")
unsignedTypes = smallUnsignedTypes + ("uint64_t",) unsignedTypes = smallUnsignedTypes + ("uint64_t",)
@ -3414,6 +3417,9 @@ let {{
twoRegMiscInst("vrev64", "NVrev64D", "SimdAluOp", smallUnsignedTypes, 2, vrev64Code) twoRegMiscInst("vrev64", "NVrev64D", "SimdAluOp", smallUnsignedTypes, 2, vrev64Code)
twoRegMiscInst("vrev64", "NVrev64Q", "SimdAluOp", smallUnsignedTypes, 4, vrev64Code) twoRegMiscInst("vrev64", "NVrev64Q", "SimdAluOp", smallUnsignedTypes, 4, vrev64Code)
split('exec')
exec_output += vcompares + vcomparesL
vpaddlCode = ''' vpaddlCode = '''
destElem = (BigElement)srcElem1 + (BigElement)srcElem2; destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
''' '''

3
src/arch/arm/isa/insts/neon64.isa
View file

@ -1959,6 +1959,9 @@ let {{
2, minAcrossCode) 2, minAcrossCode)
twoRegAcrossInstX("sminv", "SminvQX", "SimdCmpOp", smallSignedTypes, 4, twoRegAcrossInstX("sminv", "SminvQX", "SimdCmpOp", smallSignedTypes, 4,
minAcrossCode) minAcrossCode)
split('exec')
# SMLAL, SMLAL2 (by element) # SMLAL, SMLAL2 (by element)
mlalCode = "destElem += (BigElement)srcElem1 * (BigElement)srcElem2;" mlalCode = "destElem += (BigElement)srcElem1 * (BigElement)srcElem2;"
threeRegLongInstX("smlal", "SmlalElemX", "SimdMultAccOp", threeRegLongInstX("smlal", "SmlalElemX", "SimdMultAccOp",