arm, configs: Do not forward snoops from I cache
This fix simply tells the I cache to not forward snoops to the fetch unit (since there is really no reason to do so).
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1 changed files with 5 additions and 4 deletions
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@ -150,7 +150,8 @@ class O3_ARM_v7a_ICache(BaseCache):
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tgts_per_mshr = 8
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tgts_per_mshr = 8
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size = '32kB'
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size = '32kB'
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assoc = 2
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assoc = 2
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is_top_level = 'true'
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is_top_level = True
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forward_snoops = False
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# Data Cache
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# Data Cache
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class O3_ARM_v7a_DCache(BaseCache):
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class O3_ARM_v7a_DCache(BaseCache):
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@ -161,7 +162,7 @@ class O3_ARM_v7a_DCache(BaseCache):
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size = '32kB'
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size = '32kB'
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assoc = 2
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assoc = 2
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write_buffers = 16
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write_buffers = 16
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is_top_level = 'true'
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is_top_level = True
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# TLB Cache
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# TLB Cache
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# Use a cache as a L2 TLB
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# Use a cache as a L2 TLB
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@ -173,7 +174,7 @@ class O3_ARM_v7aWalkCache(BaseCache):
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size = '1kB'
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size = '1kB'
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assoc = 8
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assoc = 8
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write_buffers = 16
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write_buffers = 16
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is_top_level = 'true'
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is_top_level = True
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# L2 Cache
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# L2 Cache
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@ -185,7 +186,7 @@ class O3_ARM_v7aL2(BaseCache):
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size = '1MB'
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size = '1MB'
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assoc = 16
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assoc = 16
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write_buffers = 8
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write_buffers = 8
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prefetch_on_access = 'true'
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prefetch_on_access = True
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# Simple stride prefetcher
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# Simple stride prefetcher
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prefetcher = StridePrefetcher(degree=8, latency = 1)
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prefetcher = StridePrefetcher(degree=8, latency = 1)
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tags = RandomRepl()
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tags = RandomRepl()
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