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arm: compute ID_AA64PFR{0,1}_EL1 registers

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Compute the proper values of the aforementioned registers from
the system configuration rather than configuring the values themselves.

Change-Id: If9774b6610a29568b80ae4866107b9a6a5b5be0f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Curtis Dunham 2016-12-19 11:03:28 -06:00
parent a73937b60c
commit ae2e0ca3d0
2 changed files with 7 additions and 9 deletions
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7
src/arch/arm/ArmISA.py
View file

@ -106,10 +106,3 @@ class ArmISA(SimObject):
# Reserved for future expansion
id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Memory Model Feature Register 1")
# !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
id_aa64pfr0_el1 = Param.UInt64(0x0000000000000022,
"AArch64 Processor Feature Register 0")
# Reserved for future expansion
id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Processor Feature Register 1")

9
src/arch/arm/isa.cc
View file

@ -452,8 +452,6 @@ ISA::clear64(const ArmISAParams *p)
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
miscRegs[MISCREG_ID_DFR0_EL1] =
(p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
@ -776,6 +774,13 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
return 0x00000001
| (haveSecurity ? 0x00000010 : 0x0)
| (haveVirtualization ? 0x00001000 : 0x0);
case MISCREG_ID_AA64PFR0_EL1:
return 0x0000000000000002 // AArch{64,32} supported at EL0
| 0x0000000000000020 // EL1
| (haveVirtualization ? 0x0000000000000200 : 0) // EL2
| (haveSecurity ? 0x0000000000002000 : 0); // EL3
case MISCREG_ID_AA64PFR1_EL1:
return 0; // bits [63:0] RES0 (reserved for future use)
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: