split uart into urt8250 and uart8530
fix some doxygen comments SConscript: Added split uart files dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/tsunami.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/tsunamireg.h: fix doxgyen file comment dev/uart.cc: dev/uart.hh: python/m5/objects/Uart.py: split uart into urt8250 and uart8530 --HG-- extra : convert_revision : 2e70aad892a37620d7909017648bca6d7d69d678
This commit is contained in:
parent
8bbaaa7478
commit
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14 changed files with 469 additions and 436 deletions
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@ -293,6 +293,8 @@ full_system_sources = Split('''
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dev/tsunami_io.cc
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dev/tsunami_io.cc
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dev/tsunami_pchip.cc
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dev/tsunami_pchip.cc
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dev/uart.cc
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dev/uart.cc
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dev/uart8530.cc
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dev/uart8250.cc
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kern/kernel_binning.cc
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kern/kernel_binning.cc
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kern/kernel_stats.cc
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kern/kernel_stats.cc
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Device module for modelling the National Semiconductor
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* Device module for modelling the National Semiconductor
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* DP83820 ethernet controller. Does not support priority queueing
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* DP83820 ethernet controller. Does not support priority queueing
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*/
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*/
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Device module for modelling the National Semiconductor
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* Device module for modelling the National Semiconductor
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* DP83820 ethernet controller
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* DP83820 ethernet controller
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*/
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*/
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Ethernet device register definitions for the National
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* Ethernet device register definitions for the National
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* Semiconductor DP83820 Ethernet controller
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* Semiconductor DP83820 Ethernet controller
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*/
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*/
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@ -26,6 +26,9 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/** @file Implementation of Tsunami platform.
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*/
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#include <deque>
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#include <deque>
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#include <string>
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#include <string>
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#include <vector>
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#include <vector>
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Emulation of the Tsunami CChip CSRs
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* Emulation of the Tsunami CChip CSRs
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*/
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*/
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Tsunami I/O including PIC, PIT, RTC, DMA
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* Tsunami I/O including PIC, PIT, RTC, DMA
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*/
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*/
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Tsunami PChip (pci)
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* Tsunami PChip (pci)
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*/
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*/
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@ -26,6 +26,10 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/** @file
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* List of Tsunami CSRs
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*/
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#ifndef __TSUNAMIREG_H__
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#ifndef __TSUNAMIREG_H__
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#define __TSUNAMIREG_H__
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#define __TSUNAMIREG_H__
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399
dev/uart.cc
399
dev/uart.cc
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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/* @file
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/** @file
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* Implements a 8250 UART
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* Implements a 8250 UART
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*/
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*/
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@ -47,60 +47,9 @@
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using namespace std;
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using namespace std;
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Uart::IntrEvent::IntrEvent(Uart *u, int bit)
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: Event(&mainEventQueue), uart(u)
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{
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DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
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intrBit = bit;
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}
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const char *
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Uart::IntrEvent::description()
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{
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return "uart interrupt delay event";
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}
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void
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Uart::IntrEvent::process()
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{
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if (intrBit & uart->IER) {
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DPRINTF(Uart, "UART InterEvent, interrupting\n");
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uart->platform->postConsoleInt();
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uart->status |= intrBit;
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}
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else
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DPRINTF(Uart, "UART InterEvent, not interrupting\n");
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}
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/* The linux serial driver (8250.c about line 1182) loops reading from
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* the device until the device reports it has no more data to
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* read. After a maximum of 255 iterations the code prints "serial8250
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* too much work for irq X," and breaks out of the loop. Since the
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* simulated system is so much slower than the actual system, if a
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* user is typing on the keyboard it is very easy for them to provide
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* input at a fast enough rate to not allow the loop to exit and thus
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* the error to be printed. This magic number provides a delay between
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* the time the UART receives a character to send to the simulated
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* system and the time it actually notifies the system it has a
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* character to send to alleviate this problem. --Ali
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*/
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void
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Uart::IntrEvent::scheduleIntr()
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{
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static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
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DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
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curTick + interval);
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if (!scheduled())
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schedule(curTick + interval);
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else
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reschedule(curTick + interval);
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}
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Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
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Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
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: PioDevice(name, p), addr(a), size(s), cons(c),
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: PioDevice(name, p), addr(a), size(s), cons(c)
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txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
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{
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{
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mmu->add_child(this, RangeSize(addr, size));
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mmu->add_child(this, RangeSize(addr, size));
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@ -112,270 +61,11 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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pioLatency = pio_latency * bus->clockRate;
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pioLatency = pio_latency * bus->clockRate;
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}
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}
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readAddr = 0;
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IER = 0;
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DLAB = 0;
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LCR = 0;
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MCR = 0;
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status = 0;
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status = 0;
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// set back pointers
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// set back pointers
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cons->uart = this;
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cons->uart = this;
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platform->uart = this;
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platform->uart = this;
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}
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Fault
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Uart::read(MemReqPtr &req, uint8_t *data)
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{
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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DPRINTF(Uart, " read register %#x\n", daddr);
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#ifdef ALPHA_TLASER
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switch (req->size) {
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case sizeof(uint64_t):
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*(uint64_t *)data = 0;
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break;
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case sizeof(uint32_t):
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*(uint32_t *)data = 0;
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break;
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case sizeof(uint16_t):
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*(uint16_t *)data = 0;
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break;
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case sizeof(uint8_t):
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*(uint8_t *)data = 0;
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break;
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}
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switch (daddr) {
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case 0x80: // Status Register
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if (readAddr == 3) {
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readAddr = 0;
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if (status & TX_INT)
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*data = (1 << 4);
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else if (status & RX_INT)
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*data = (1 << 5);
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else
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DPRINTF(Uart, "spurious read\n");
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} else {
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*data = (1 << 2);
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if (status & RX_INT)
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*data |= (1 << 0);
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}
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break;
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case 0xc0: // Data register (RX)
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if (!cons->dataAvailable())
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panic("No data to read");
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cons->in(*data);
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if (!cons->dataAvailable()) {
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platform->clearConsoleInt();
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status &= ~RX_INT;
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}
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DPRINTF(Uart, "read data register \'%c\' %2x\n",
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isprint(*data) ? *data : ' ', *data);
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break;
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}
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#else
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assert(req->size == 1);
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // read byte
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if (cons->dataAvailable())
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cons->in(*data);
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else {
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*(uint8_t*)data = 0;
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// A limited amount of these are ok.
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DPRINTF(Uart, "empty read of RX register\n");
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}
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status &= ~RX_INT;
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platform->clearConsoleInt();
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if (cons->dataAvailable() && (IER & UART_IER_RDI))
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rxIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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*(uint8_t*)data = IER;
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // Intr Identification Register (IIR)
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DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
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if (status)
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*(uint8_t*)data = 0;
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else
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*(uint8_t*)data = 1;
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break;
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case 0x3: // Line Control Register (LCR)
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*(uint8_t*)data = LCR;
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break;
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case 0x4: // Modem Control Register (MCR)
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break;
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case 0x5: // Line Status Register (LSR)
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uint8_t lsr;
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lsr = 0;
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// check if there are any bytes to be read
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if (cons->dataAvailable())
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lsr = UART_LSR_DR;
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lsr |= UART_LSR_TEMT | UART_LSR_THRE;
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*(uint8_t*)data = lsr;
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break;
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case 0x6: // Modem Status Register (MSR)
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*(uint8_t*)data = 0;
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break;
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case 0x7: // Scratch Register (SCR)
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*(uint8_t*)data = 0; // doesn't exist with at 8250.
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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#endif
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return No_Fault;
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}
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Fault
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Uart::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
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#ifdef ALPHA_TLASER
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switch (daddr) {
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case 0x80:
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readAddr = *data;
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switch (*data) {
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case 0x28: // Ack of TX
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if ((status & TX_INT) == 0)
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panic("Ack of transmit, though there was no interrupt");
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status &= ~TX_INT;
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platform->clearConsoleInt();
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break;
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case 0x00:
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case 0x01:
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case 0x03: // going to read RR3
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case 0x12:
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break;
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default:
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DPRINTF(Uart, "writing status register %#x \n",
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*(uint64_t *)data);
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break;
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}
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break;
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case 0xc0: // Data register (TX)
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cons->out(*(uint64_t *)data);
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platform->postConsoleInt();
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status |= TX_INT;
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break;
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}
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#else
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // write byte
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cons->out(*(uint8_t *)data);
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platform->clearConsoleInt();
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status &= ~TX_INT;
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if (UART_IER_THRI & IER)
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txIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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IER = *(uint8_t*)data;
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if (UART_IER_THRI & IER)
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{
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DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
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txIntrEvent.scheduleIntr();
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}
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else
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{
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DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
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if (txIntrEvent.scheduled())
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txIntrEvent.deschedule();
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if (status & TX_INT)
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platform->clearConsoleInt();
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status &= ~TX_INT;
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}
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if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
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DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
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rxIntrEvent.scheduleIntr();
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} else {
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DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
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if (rxIntrEvent.scheduled())
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rxIntrEvent.deschedule();
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if (status & RX_INT)
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platform->clearConsoleInt();
|
|
||||||
status &= ~RX_INT;
|
|
||||||
}
|
|
||||||
} else { // DLM divisor latch MSB
|
|
||||||
;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 0x2: // FIFO Control Register (FCR)
|
|
||||||
break;
|
|
||||||
case 0x3: // Line Control Register (LCR)
|
|
||||||
LCR = *(uint8_t*)data;
|
|
||||||
break;
|
|
||||||
case 0x4: // Modem Control Register (MCR)
|
|
||||||
if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
|
|
||||||
MCR = 0x9A;
|
|
||||||
break;
|
|
||||||
case 0x7: // Scratch Register (SCR)
|
|
||||||
// We are emulating a 8250 so we don't have a scratch reg
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
panic("Tried to access a UART port that doesn't exist\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return No_Fault;
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
Uart::dataAvailable()
|
|
||||||
{
|
|
||||||
#ifdef ALPHA_TLASER
|
|
||||||
platform->postConsoleInt();
|
|
||||||
status |= RX_INT;
|
|
||||||
#else
|
|
||||||
|
|
||||||
// if the kernel wants an interrupt when we have data
|
|
||||||
if (IER & UART_IER_RDI)
|
|
||||||
{
|
|
||||||
platform->postConsoleInt();
|
|
||||||
status |= RX_INT;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
Tick
|
Tick
|
||||||
|
@ -384,88 +74,5 @@ Uart::cacheAccess(MemReqPtr &req)
|
||||||
return curTick + pioLatency;
|
return curTick + pioLatency;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
|
||||||
Uart::serialize(ostream &os)
|
|
||||||
{
|
|
||||||
#ifdef ALPHA_TLASER
|
|
||||||
SERIALIZE_SCALAR(readAddr);
|
|
||||||
SERIALIZE_SCALAR(status);
|
|
||||||
#else
|
|
||||||
SERIALIZE_SCALAR(status);
|
|
||||||
SERIALIZE_SCALAR(IER);
|
|
||||||
SERIALIZE_SCALAR(DLAB);
|
|
||||||
SERIALIZE_SCALAR(LCR);
|
|
||||||
SERIALIZE_SCALAR(MCR);
|
|
||||||
Tick rxintrwhen;
|
|
||||||
if (rxIntrEvent.scheduled())
|
|
||||||
rxintrwhen = rxIntrEvent.when();
|
|
||||||
else
|
|
||||||
rxintrwhen = 0;
|
|
||||||
Tick txintrwhen;
|
|
||||||
if (txIntrEvent.scheduled())
|
|
||||||
txintrwhen = txIntrEvent.when();
|
|
||||||
else
|
|
||||||
txintrwhen = 0;
|
|
||||||
SERIALIZE_SCALAR(rxintrwhen);
|
|
||||||
SERIALIZE_SCALAR(txintrwhen);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
Uart::unserialize(Checkpoint *cp, const std::string §ion)
|
|
||||||
{
|
|
||||||
#ifdef ALPHA_TLASER
|
|
||||||
UNSERIALIZE_SCALAR(readAddr);
|
|
||||||
UNSERIALIZE_SCALAR(status);
|
|
||||||
#else
|
|
||||||
UNSERIALIZE_SCALAR(status);
|
|
||||||
UNSERIALIZE_SCALAR(IER);
|
|
||||||
UNSERIALIZE_SCALAR(DLAB);
|
|
||||||
UNSERIALIZE_SCALAR(LCR);
|
|
||||||
UNSERIALIZE_SCALAR(MCR);
|
|
||||||
Tick rxintrwhen;
|
|
||||||
Tick txintrwhen;
|
|
||||||
UNSERIALIZE_SCALAR(rxintrwhen);
|
|
||||||
UNSERIALIZE_SCALAR(txintrwhen);
|
|
||||||
if (rxintrwhen != 0)
|
|
||||||
rxIntrEvent.schedule(rxintrwhen);
|
|
||||||
if (txintrwhen != 0)
|
|
||||||
txIntrEvent.schedule(txintrwhen);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart)
|
|
||||||
|
|
||||||
SimObjectParam<SimConsole *> console;
|
|
||||||
SimObjectParam<MemoryController *> mmu;
|
|
||||||
SimObjectParam<Platform *> platform;
|
|
||||||
Param<Addr> addr;
|
|
||||||
Param<Addr> size;
|
|
||||||
SimObjectParam<Bus*> io_bus;
|
|
||||||
Param<Tick> pio_latency;
|
|
||||||
SimObjectParam<HierParams *> hier;
|
|
||||||
|
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(Uart)
|
|
||||||
|
|
||||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart)
|
|
||||||
|
|
||||||
INIT_PARAM(console, "The console"),
|
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
|
||||||
INIT_PARAM(platform, "Pointer to platfrom"),
|
|
||||||
INIT_PARAM(addr, "Device Address"),
|
|
||||||
INIT_PARAM_DFLT(size, "Device size", 0x8),
|
|
||||||
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
|
||||||
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
|
||||||
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(Uart)
|
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(Uart)
|
|
||||||
{
|
|
||||||
return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
|
|
||||||
pio_latency, platform);
|
|
||||||
}
|
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("Uart", Uart)
|
|
||||||
|
|
44
dev/uart.hh
44
dev/uart.hh
|
@ -26,14 +26,13 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* @file
|
/** @file
|
||||||
* Defines a 8250 UART
|
* Base class for UART
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __TSUNAMI_UART_HH__
|
#ifndef __UART_HH__
|
||||||
#define __TSUNAMI_UART_HH__
|
#define __UART_HH__
|
||||||
|
|
||||||
#include "dev/tsunamireg.h"
|
|
||||||
#include "base/range.hh"
|
#include "base/range.hh"
|
||||||
#include "dev/io_device.hh"
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
|
@ -47,45 +46,25 @@ const int TX_INT = 0x2;
|
||||||
class Uart : public PioDevice
|
class Uart : public PioDevice
|
||||||
{
|
{
|
||||||
|
|
||||||
private:
|
protected:
|
||||||
|
int status;
|
||||||
Addr addr;
|
Addr addr;
|
||||||
Addr size;
|
Addr size;
|
||||||
SimConsole *cons;
|
SimConsole *cons;
|
||||||
|
|
||||||
|
|
||||||
protected:
|
|
||||||
int readAddr; // tlaser only
|
|
||||||
uint8_t IER, DLAB, LCR, MCR;
|
|
||||||
int status;
|
|
||||||
|
|
||||||
class IntrEvent : public Event
|
|
||||||
{
|
|
||||||
protected:
|
|
||||||
Uart *uart;
|
|
||||||
int intrBit;
|
|
||||||
public:
|
|
||||||
IntrEvent(Uart *u, int bit);
|
|
||||||
virtual void process();
|
|
||||||
virtual const char *description();
|
|
||||||
void scheduleIntr();
|
|
||||||
};
|
|
||||||
|
|
||||||
IntrEvent txIntrEvent;
|
|
||||||
IntrEvent rxIntrEvent;
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
|
Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
|
||||||
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
|
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
|
||||||
Platform *p);
|
Platform *p);
|
||||||
|
|
||||||
Fault read(MemReqPtr &req, uint8_t *data);
|
virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
|
||||||
Fault write(MemReqPtr &req, const uint8_t *data);
|
virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Inform the uart that there is data available.
|
* Inform the uart that there is data available.
|
||||||
*/
|
*/
|
||||||
void dataAvailable();
|
virtual void dataAvailable() = 0;
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -94,9 +73,6 @@ class Uart : public PioDevice
|
||||||
*/
|
*/
|
||||||
bool intStatus() { return status ? true : false; }
|
bool intStatus() { return status ? true : false; }
|
||||||
|
|
||||||
virtual void serialize(std::ostream &os);
|
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Return how long this access will take.
|
* Return how long this access will take.
|
||||||
* @param req the memory request to calcuate
|
* @param req the memory request to calcuate
|
||||||
|
@ -105,4 +81,4 @@ class Uart : public PioDevice
|
||||||
Tick cacheAccess(MemReqPtr &req);
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __TSUNAMI_UART_HH__
|
#endif // __UART_HH__
|
||||||
|
|
341
dev/uart8250.cc
Normal file
341
dev/uart8250.cc
Normal file
|
@ -0,0 +1,341 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @file
|
||||||
|
* Implements a 8250 UART
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string>
|
||||||
|
#include <vector>
|
||||||
|
|
||||||
|
#include "base/inifile.hh"
|
||||||
|
#include "base/str.hh" // for to_number
|
||||||
|
#include "base/trace.hh"
|
||||||
|
#include "dev/simconsole.hh"
|
||||||
|
#include "dev/uart8250.hh"
|
||||||
|
#include "dev/platform.hh"
|
||||||
|
#include "mem/bus/bus.hh"
|
||||||
|
#include "mem/bus/pio_interface.hh"
|
||||||
|
#include "mem/bus/pio_interface_impl.hh"
|
||||||
|
#include "mem/functional_mem/memory_control.hh"
|
||||||
|
#include "sim/builder.hh"
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
|
||||||
|
Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
|
||||||
|
: Event(&mainEventQueue), uart(u)
|
||||||
|
{
|
||||||
|
DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
|
||||||
|
intrBit = bit;
|
||||||
|
}
|
||||||
|
|
||||||
|
const char *
|
||||||
|
Uart8250::IntrEvent::description()
|
||||||
|
{
|
||||||
|
return "uart interrupt delay event";
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
Uart8250::IntrEvent::process()
|
||||||
|
{
|
||||||
|
if (intrBit & uart->IER) {
|
||||||
|
DPRINTF(Uart, "UART InterEvent, interrupting\n");
|
||||||
|
uart->platform->postConsoleInt();
|
||||||
|
uart->status |= intrBit;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The linux serial driver (8250.c about line 1182) loops reading from
|
||||||
|
* the device until the device reports it has no more data to
|
||||||
|
* read. After a maximum of 255 iterations the code prints "serial8250
|
||||||
|
* too much work for irq X," and breaks out of the loop. Since the
|
||||||
|
* simulated system is so much slower than the actual system, if a
|
||||||
|
* user is typing on the keyboard it is very easy for them to provide
|
||||||
|
* input at a fast enough rate to not allow the loop to exit and thus
|
||||||
|
* the error to be printed. This magic number provides a delay between
|
||||||
|
* the time the UART receives a character to send to the simulated
|
||||||
|
* system and the time it actually notifies the system it has a
|
||||||
|
* character to send to alleviate this problem. --Ali
|
||||||
|
*/
|
||||||
|
void
|
||||||
|
Uart8250::IntrEvent::scheduleIntr()
|
||||||
|
{
|
||||||
|
static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
|
||||||
|
DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
|
||||||
|
curTick + interval);
|
||||||
|
if (!scheduled())
|
||||||
|
schedule(curTick + interval);
|
||||||
|
else
|
||||||
|
reschedule(curTick + interval);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
|
||||||
|
Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
|
||||||
|
: Uart(name, c, mmu, a, s, hier, bus, pio_latency, p),
|
||||||
|
txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
|
||||||
|
{
|
||||||
|
IER = 0;
|
||||||
|
DLAB = 0;
|
||||||
|
LCR = 0;
|
||||||
|
MCR = 0;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault
|
||||||
|
Uart8250::read(MemReqPtr &req, uint8_t *data)
|
||||||
|
{
|
||||||
|
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
|
||||||
|
DPRINTF(Uart, " read register %#x\n", daddr);
|
||||||
|
|
||||||
|
assert(req->size == 1);
|
||||||
|
|
||||||
|
switch (daddr) {
|
||||||
|
case 0x0:
|
||||||
|
if (!(LCR & 0x80)) { // read byte
|
||||||
|
if (cons->dataAvailable())
|
||||||
|
cons->in(*data);
|
||||||
|
else {
|
||||||
|
*(uint8_t*)data = 0;
|
||||||
|
// A limited amount of these are ok.
|
||||||
|
DPRINTF(Uart, "empty read of RX register\n");
|
||||||
|
}
|
||||||
|
status &= ~RX_INT;
|
||||||
|
platform->clearConsoleInt();
|
||||||
|
|
||||||
|
if (cons->dataAvailable() && (IER & UART_IER_RDI))
|
||||||
|
rxIntrEvent.scheduleIntr();
|
||||||
|
} else { // dll divisor latch
|
||||||
|
;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 0x1:
|
||||||
|
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
||||||
|
*(uint8_t*)data = IER;
|
||||||
|
} else { // DLM divisor latch MSB
|
||||||
|
;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 0x2: // Intr Identification Register (IIR)
|
||||||
|
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
|
||||||
|
if (status)
|
||||||
|
*(uint8_t*)data = 0;
|
||||||
|
else
|
||||||
|
*(uint8_t*)data = 1;
|
||||||
|
break;
|
||||||
|
case 0x3: // Line Control Register (LCR)
|
||||||
|
*(uint8_t*)data = LCR;
|
||||||
|
break;
|
||||||
|
case 0x4: // Modem Control Register (MCR)
|
||||||
|
break;
|
||||||
|
case 0x5: // Line Status Register (LSR)
|
||||||
|
uint8_t lsr;
|
||||||
|
lsr = 0;
|
||||||
|
// check if there are any bytes to be read
|
||||||
|
if (cons->dataAvailable())
|
||||||
|
lsr = UART_LSR_DR;
|
||||||
|
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
|
||||||
|
*(uint8_t*)data = lsr;
|
||||||
|
break;
|
||||||
|
case 0x6: // Modem Status Register (MSR)
|
||||||
|
*(uint8_t*)data = 0;
|
||||||
|
break;
|
||||||
|
case 0x7: // Scratch Register (SCR)
|
||||||
|
*(uint8_t*)data = 0; // doesn't exist with at 8250.
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Tried to access a UART port that doesn't exist\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return No_Fault;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
Fault
|
||||||
|
Uart8250::write(MemReqPtr &req, const uint8_t *data)
|
||||||
|
{
|
||||||
|
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
|
||||||
|
|
||||||
|
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
||||||
|
|
||||||
|
switch (daddr) {
|
||||||
|
case 0x0:
|
||||||
|
if (!(LCR & 0x80)) { // write byte
|
||||||
|
cons->out(*(uint8_t *)data);
|
||||||
|
platform->clearConsoleInt();
|
||||||
|
status &= ~TX_INT;
|
||||||
|
if (UART_IER_THRI & IER)
|
||||||
|
txIntrEvent.scheduleIntr();
|
||||||
|
} else { // dll divisor latch
|
||||||
|
;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 0x1:
|
||||||
|
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
||||||
|
IER = *(uint8_t*)data;
|
||||||
|
if (UART_IER_THRI & IER)
|
||||||
|
{
|
||||||
|
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
|
||||||
|
txIntrEvent.scheduleIntr();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
|
||||||
|
if (txIntrEvent.scheduled())
|
||||||
|
txIntrEvent.deschedule();
|
||||||
|
if (status & TX_INT)
|
||||||
|
platform->clearConsoleInt();
|
||||||
|
status &= ~TX_INT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
|
||||||
|
DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
|
||||||
|
rxIntrEvent.scheduleIntr();
|
||||||
|
} else {
|
||||||
|
DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
|
||||||
|
if (rxIntrEvent.scheduled())
|
||||||
|
rxIntrEvent.deschedule();
|
||||||
|
if (status & RX_INT)
|
||||||
|
platform->clearConsoleInt();
|
||||||
|
status &= ~RX_INT;
|
||||||
|
}
|
||||||
|
} else { // DLM divisor latch MSB
|
||||||
|
;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 0x2: // FIFO Control Register (FCR)
|
||||||
|
break;
|
||||||
|
case 0x3: // Line Control Register (LCR)
|
||||||
|
LCR = *(uint8_t*)data;
|
||||||
|
break;
|
||||||
|
case 0x4: // Modem Control Register (MCR)
|
||||||
|
if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
|
||||||
|
MCR = 0x9A;
|
||||||
|
break;
|
||||||
|
case 0x7: // Scratch Register (SCR)
|
||||||
|
// We are emulating a 8250 so we don't have a scratch reg
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
panic("Tried to access a UART port that doesn't exist\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return No_Fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
Uart8250::dataAvailable()
|
||||||
|
{
|
||||||
|
// if the kernel wants an interrupt when we have data
|
||||||
|
if (IER & UART_IER_RDI)
|
||||||
|
{
|
||||||
|
platform->postConsoleInt();
|
||||||
|
status |= RX_INT;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void
|
||||||
|
Uart8250::serialize(ostream &os)
|
||||||
|
{
|
||||||
|
SERIALIZE_SCALAR(status);
|
||||||
|
SERIALIZE_SCALAR(IER);
|
||||||
|
SERIALIZE_SCALAR(DLAB);
|
||||||
|
SERIALIZE_SCALAR(LCR);
|
||||||
|
SERIALIZE_SCALAR(MCR);
|
||||||
|
Tick rxintrwhen;
|
||||||
|
if (rxIntrEvent.scheduled())
|
||||||
|
rxintrwhen = rxIntrEvent.when();
|
||||||
|
else
|
||||||
|
rxintrwhen = 0;
|
||||||
|
Tick txintrwhen;
|
||||||
|
if (txIntrEvent.scheduled())
|
||||||
|
txintrwhen = txIntrEvent.when();
|
||||||
|
else
|
||||||
|
txintrwhen = 0;
|
||||||
|
SERIALIZE_SCALAR(rxintrwhen);
|
||||||
|
SERIALIZE_SCALAR(txintrwhen);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
Uart8250::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
{
|
||||||
|
UNSERIALIZE_SCALAR(status);
|
||||||
|
UNSERIALIZE_SCALAR(IER);
|
||||||
|
UNSERIALIZE_SCALAR(DLAB);
|
||||||
|
UNSERIALIZE_SCALAR(LCR);
|
||||||
|
UNSERIALIZE_SCALAR(MCR);
|
||||||
|
Tick rxintrwhen;
|
||||||
|
Tick txintrwhen;
|
||||||
|
UNSERIALIZE_SCALAR(rxintrwhen);
|
||||||
|
UNSERIALIZE_SCALAR(txintrwhen);
|
||||||
|
if (rxintrwhen != 0)
|
||||||
|
rxIntrEvent.schedule(rxintrwhen);
|
||||||
|
if (txintrwhen != 0)
|
||||||
|
txIntrEvent.schedule(txintrwhen);
|
||||||
|
}
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
|
SimObjectParam<SimConsole *> console;
|
||||||
|
SimObjectParam<MemoryController *> mmu;
|
||||||
|
SimObjectParam<Platform *> platform;
|
||||||
|
Param<Addr> addr;
|
||||||
|
Param<Addr> size;
|
||||||
|
SimObjectParam<Bus*> io_bus;
|
||||||
|
Param<Tick> pio_latency;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
|
INIT_PARAM(console, "The console"),
|
||||||
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
|
INIT_PARAM(platform, "Pointer to platfrom"),
|
||||||
|
INIT_PARAM(addr, "Device Address"),
|
||||||
|
INIT_PARAM_DFLT(size, "Device size", 0x8),
|
||||||
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(Uart8250)
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(Uart8250)
|
||||||
|
{
|
||||||
|
return new Uart8250(getInstanceName(), console, mmu, addr, size, hier, io_bus,
|
||||||
|
pio_latency, platform);
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("Uart8250", Uart8250)
|
92
dev/uart8250.hh
Normal file
92
dev/uart8250.hh
Normal file
|
@ -0,0 +1,92 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @file
|
||||||
|
* Defines a 8250 UART
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __TSUNAMI_UART_HH__
|
||||||
|
#define __TSUNAMI_UART_HH__
|
||||||
|
|
||||||
|
#include "dev/tsunamireg.h"
|
||||||
|
#include "base/range.hh"
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
#include "dev/uart.hh"
|
||||||
|
|
||||||
|
class SimConsole;
|
||||||
|
class Platform;
|
||||||
|
|
||||||
|
class Uart8250 : public Uart
|
||||||
|
{
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
uint8_t IER, DLAB, LCR, MCR;
|
||||||
|
|
||||||
|
class IntrEvent : public Event
|
||||||
|
{
|
||||||
|
protected:
|
||||||
|
Uart8250 *uart;
|
||||||
|
int intrBit;
|
||||||
|
public:
|
||||||
|
IntrEvent(Uart8250 *u, int bit);
|
||||||
|
virtual void process();
|
||||||
|
virtual const char *description();
|
||||||
|
void scheduleIntr();
|
||||||
|
};
|
||||||
|
|
||||||
|
IntrEvent txIntrEvent;
|
||||||
|
IntrEvent rxIntrEvent;
|
||||||
|
|
||||||
|
public:
|
||||||
|
Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
|
||||||
|
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
|
||||||
|
Platform *p);
|
||||||
|
|
||||||
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
||||||
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Inform the uart that there is data available.
|
||||||
|
*/
|
||||||
|
virtual void dataAvailable();
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Return if we have an interrupt pending
|
||||||
|
* @return interrupt status
|
||||||
|
*/
|
||||||
|
virtual bool intStatus() { return status ? true : false; }
|
||||||
|
|
||||||
|
virtual void serialize(std::ostream &os);
|
||||||
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __TSUNAMI_UART_HH__
|
|
@ -3,5 +3,13 @@ from Device import PioDevice
|
||||||
|
|
||||||
class Uart(PioDevice):
|
class Uart(PioDevice):
|
||||||
type = 'Uart'
|
type = 'Uart'
|
||||||
|
abstract = True
|
||||||
console = Param.SimConsole(Parent.any, "The console")
|
console = Param.SimConsole(Parent.any, "The console")
|
||||||
size = Param.Addr(0x8, "Device size")
|
size = Param.Addr(0x8, "Device size")
|
||||||
|
|
||||||
|
class Uart8250(Uart):
|
||||||
|
type = 'Uart8250'
|
||||||
|
|
||||||
|
class Uart8530(Uart):
|
||||||
|
type = 'Uart8530'
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue