sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Merge zizzer:/z/m5/Bitkeeper/newmem

Browse source 
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : c811eb9eacc480b14862f8074af80c56ec1e07f1
This commit is contained in:
Ron Dreslinski 2006-07-10 17:19:54 -04:00
parent 185a5502b7 6592045cbc
commit ad4374e0cd
3 changed files with 20 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
src/mem/cache/base_cache.cc vendored
View file

@ -117,11 +117,24 @@ BaseCache::CacheEvent::process()
if (!pkt) if (!pkt)
{ {
if (!cachePort->isCpuSide) if (!cachePort->isCpuSide)
{
pkt = cachePort->cache->getPacket(); pkt = cachePort->cache->getPacket();
bool success = cachePort->sendTiming(pkt);
DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
pkt->getAddr(), success ? "succesful" : "unsuccesful");
cachePort->cache->sendResult(pkt, success);
if (success && cachePort->cache->doMasterRequest())
{
//Still more to issue, rerequest in 1 cycle
pkt = NULL;
this->schedule(curTick+1);
}
}
else else
{
pkt = cachePort->cache->getCoherencePacket(); pkt = cachePort->cache->getCoherencePacket();
bool success = cachePort->sendTiming(pkt); cachePort->sendTiming(pkt);
cachePort->cache->sendResult(pkt, success); }
return; return;
} }
//Know the packet to send, no need to mark in service (must succed) //Know the packet to send, no need to mark in service (must succed)

8
src/mem/cache/miss/miss_queue.cc vendored
View file

@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
MSHR* MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time) MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
{ {
MSHR* mshr = mq.allocate(pkt, size); MSHR* mshr = mq.allocate(pkt, blkSize);
mshr->order = order++; mshr->order = order++;
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) { if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
// Mark this as a cache line fill // Mark this as a cache line fill
@ -372,7 +372,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
MSHR* MSHR*
MissQueue::allocateWrite(Packet * &pkt, int size, Tick time) MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
{ {
MSHR* mshr = wb.allocate(pkt,pkt->getSize()); MSHR* mshr = wb.allocate(pkt,blkSize);
mshr->order = order++; mshr->order = order++;
//REMOVING COMPRESSION FOR NOW //REMOVING COMPRESSION FOR NOW
@ -446,11 +446,11 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
/** /**
* @todo Add write merging here. * @todo Add write merging here.
*/ */
mshr = allocateWrite(pkt, pkt->getSize(), time); mshr = allocateWrite(pkt, blkSize, time);
return; return;
} }
mshr = allocateMiss(pkt, size, time); mshr = allocateMiss(pkt, blkSize, time);
} }
MSHR* MSHR*

1
src/mem/cache/miss/mshr.cc vendored
View file

@ -57,6 +57,7 @@ void
MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size, MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
Packet * &target) Packet * &target)
{ {
addr = _addr;
if (target) if (target)
{ {
//Have a request, just use it //Have a request, just use it