CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag
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@ -268,7 +268,8 @@ class SimpleThread : public ThreadState
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int flatIndex = isa.flattenIntIndex(reg_idx);
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int flatIndex = isa.flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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assert(flatIndex < TheISA::NumIntRegs);
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uint64_t regVal = intRegs[flatIndex];
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uint64_t regVal = intRegs[flatIndex];
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DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
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DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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return regVal;
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}
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}
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@ -277,8 +278,8 @@ class SimpleThread : public ThreadState
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatReg regVal = floatRegs.f[flatIndex];
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FloatReg regVal = floatRegs.f[flatIndex];
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DPRINTF(FloatRegs, "Reading float reg %d as %f, %#x.\n",
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DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
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reg_idx, regVal, floatRegs.i[flatIndex]);
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reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
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return regVal;
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return regVal;
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}
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}
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@ -287,8 +288,8 @@ class SimpleThread : public ThreadState
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatRegBits regVal = floatRegs.i[flatIndex];
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FloatRegBits regVal = floatRegs.i[flatIndex];
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DPRINTF(FloatRegs, "Reading float reg %d bits as %#x, %f.\n",
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DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
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reg_idx, regVal, floatRegs.f[flatIndex]);
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reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
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return regVal;
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return regVal;
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}
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}
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@ -296,7 +297,8 @@ class SimpleThread : public ThreadState
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{
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{
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int flatIndex = isa.flattenIntIndex(reg_idx);
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int flatIndex = isa.flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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assert(flatIndex < TheISA::NumIntRegs);
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DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
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DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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intRegs[flatIndex] = val;
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intRegs[flatIndex] = val;
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}
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}
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@ -305,8 +307,8 @@ class SimpleThread : public ThreadState
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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assert(flatIndex < TheISA::NumFloatRegs);
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floatRegs.f[flatIndex] = val;
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floatRegs.f[flatIndex] = val;
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DPRINTF(FloatRegs, "Setting float reg %d to %f, %#x.\n",
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DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
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reg_idx, val, floatRegs.i[flatIndex]);
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reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
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}
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}
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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@ -314,8 +316,8 @@ class SimpleThread : public ThreadState
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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assert(flatIndex < TheISA::NumFloatRegs);
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floatRegs.i[flatIndex] = val;
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floatRegs.i[flatIndex] = val;
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DPRINTF(FloatRegs, "Setting float reg %d bits to %#x, %#f.\n",
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DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
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reg_idx, val, floatRegs.f[flatIndex]);
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reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
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}
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}
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uint64_t readPC()
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uint64_t readPC()
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