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x86: Fix setting segment bases in real mode.

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The data size used for actually writing the base value for the segment was the
default size, but really it should set the entire value without any possible
truncation.
This commit is contained in:
Gabe Black 2014-11-17 01:00:53 -08:00
parent f8603fa120
commit aceeecb192
2 changed files with 4 additions and 4 deletions
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4
src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
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@ -145,7 +145,7 @@ def macroop JMP_FAR_REAL_M
zexti t3, t1, 15, dataSize=8 zexti t3, t1, 15, dataSize=8
slli t3, t3, 4, dataSize=8 slli t3, t3, 4, dataSize=8
wrsel cs, t1, dataSize=2 wrsel cs, t1, dataSize=2
wrbase cs, t3 wrbase cs, t3, dataSize=8
wrip t0, t2, dataSize=asz wrip t0, t2, dataSize=asz
}; };
@ -168,7 +168,7 @@ def macroop JMP_FAR_REAL_I
mov t2, t0, t2 mov t2, t0, t2
slli t3, t1, 4, dataSize=8 slli t3, t1, 4, dataSize=8
wrsel cs, t1, dataSize=2 wrsel cs, t1, dataSize=2
wrbase cs, t3 wrbase cs, t3, dataSize=8
wrip t0, t2, dataSize=asz wrip t0, t2, dataSize=asz
}; };
''' '''

4
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
View file

@ -215,7 +215,7 @@ def macroop MOV_REAL_S_R {
zexti t2, regm, 15, dataSize=8 zexti t2, regm, 15, dataSize=8
slli t3, t2, 4, dataSize=8 slli t3, t2, 4, dataSize=8
wrsel reg, regm wrsel reg, regm
wrbase reg, t3 wrbase reg, t3, dataSize=8
}; };
def macroop MOV_REAL_S_M { def macroop MOV_REAL_S_M {
@ -223,7 +223,7 @@ def macroop MOV_REAL_S_M {
zexti t2, t1, 15, dataSize=8 zexti t2, t1, 15, dataSize=8
slli t3, t2, 4, dataSize=8 slli t3, t2, 4, dataSize=8
wrsel reg, t1 wrsel reg, t1
wrbase reg, t3 wrbase reg, t3, dataSize=8
}; };
def macroop MOV_REAL_S_P { def macroop MOV_REAL_S_P {