Make the floating point zero register special handling only apply for ALPHA.
--HG-- extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
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4 changed files with 25 additions and 0 deletions
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@ -168,7 +168,9 @@ SimpleFreeList::addReg(PhysRegIndex freed_reg)
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if (freed_reg != TheISA::ZeroReg)
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if (freed_reg != TheISA::ZeroReg)
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freeIntRegs.push(freed_reg);
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freeIntRegs.push(freed_reg);
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} else if (freed_reg < numPhysicalRegs) {
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} else if (freed_reg < numPhysicalRegs) {
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#if THE_ISA == ALPHA_ISA
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if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
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if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
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#endif
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freeFloatRegs.push(freed_reg);
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freeFloatRegs.push(freed_reg);
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}
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}
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}
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}
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@ -179,7 +179,9 @@ class PhysRegFile
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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int(reg_idx), (uint64_t)val);
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int(reg_idx), (uint64_t)val);
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#if THE_ISA == ALPHA_ISA
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if (reg_idx != TheISA::ZeroReg)
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if (reg_idx != TheISA::ZeroReg)
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#endif
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floatRegFile[reg_idx].d = val;
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floatRegFile[reg_idx].d = val;
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}
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}
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@ -194,7 +196,9 @@ class PhysRegFile
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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int(reg_idx), (uint64_t)val);
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int(reg_idx), (uint64_t)val);
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#if THE_ISA == ALPHA_ISA
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if (reg_idx != TheISA::ZeroReg)
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if (reg_idx != TheISA::ZeroReg)
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#endif
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floatRegFile[reg_idx].d = val;
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floatRegFile[reg_idx].d = val;
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}
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}
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@ -165,17 +165,21 @@ SimpleRenameMap::rename(RegIndex arch_reg)
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// If it's not referencing the zero register, then rename the
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// If it's not referencing the zero register, then rename the
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// register.
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// register.
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#if THE_ISA == ALPHA_ISA
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if (arch_reg != floatZeroReg) {
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if (arch_reg != floatZeroReg) {
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#endif
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renamed_reg = freeList->getFloatReg();
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renamed_reg = freeList->getFloatReg();
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floatRenameMap[arch_reg].physical_reg = renamed_reg;
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floatRenameMap[arch_reg].physical_reg = renamed_reg;
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assert(renamed_reg < numPhysicalRegs &&
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assert(renamed_reg < numPhysicalRegs &&
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renamed_reg >= numPhysicalIntRegs);
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renamed_reg >= numPhysicalIntRegs);
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#if THE_ISA == ALPHA_ISA
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} else {
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} else {
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// Otherwise return the zero register so nothing bad happens.
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// Otherwise return the zero register so nothing bad happens.
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renamed_reg = floatZeroReg;
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renamed_reg = floatZeroReg;
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}
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}
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#endif
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} else {
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} else {
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// Subtract off the base offset for miscellaneous registers.
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// Subtract off the base offset for miscellaneous registers.
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arch_reg = arch_reg - numLogicalRegs;
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arch_reg = arch_reg - numLogicalRegs;
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@ -29,6 +29,7 @@
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* Kevin Lim
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* Kevin Lim
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*/
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*/
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#include "arch/isa_specific.hh"
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#include "cpu/o3/scoreboard.hh"
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#include "cpu/o3/scoreboard.hh"
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Scoreboard::Scoreboard(unsigned activeThreads,
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Scoreboard::Scoreboard(unsigned activeThreads,
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@ -79,11 +80,18 @@ Scoreboard::name() const
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bool
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bool
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Scoreboard::getReg(PhysRegIndex phys_reg)
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Scoreboard::getReg(PhysRegIndex phys_reg)
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{
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{
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#if THE_ISA == ALPHA_ISA
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// Always ready if int or fp zero reg.
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// Always ready if int or fp zero reg.
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if (phys_reg == zeroRegIdx ||
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if (phys_reg == zeroRegIdx ||
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phys_reg == (zeroRegIdx + numPhysicalIntRegs)) {
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phys_reg == (zeroRegIdx + numPhysicalIntRegs)) {
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return 1;
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return 1;
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}
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}
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#else
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// Always ready if int zero reg.
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if (phys_reg == zeroRegIdx) {
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return 1;
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}
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#endif
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return regScoreBoard[phys_reg];
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return regScoreBoard[phys_reg];
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}
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}
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@ -99,11 +107,18 @@ Scoreboard::setReg(PhysRegIndex phys_reg)
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void
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void
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Scoreboard::unsetReg(PhysRegIndex ready_reg)
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Scoreboard::unsetReg(PhysRegIndex ready_reg)
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{
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{
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#if THE_ISA == ALPHA_ISA
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if (ready_reg == zeroRegIdx ||
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if (ready_reg == zeroRegIdx ||
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ready_reg == (zeroRegIdx + numPhysicalIntRegs)) {
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ready_reg == (zeroRegIdx + numPhysicalIntRegs)) {
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// Don't do anything if int or fp zero reg.
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// Don't do anything if int or fp zero reg.
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return;
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return;
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}
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}
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#else
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if (ready_reg == zeroRegIdx) {
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// Don't do anything if int zero reg.
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return;
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}
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#endif
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regScoreBoard[ready_reg] = 0;
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regScoreBoard[ready_reg] = 0;
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}
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}
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