From abe14c253b64eb3c991309bf24db60103095c70d Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 16 May 2006 14:47:09 -0400 Subject: [PATCH] Include checker and trap latency parameters. --HG-- extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42 --- python/m5/objects/AlphaFullCPU.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py index 284398b0e..1541b9494 100644 --- a/python/m5/objects/AlphaFullCPU.py +++ b/python/m5/objects/AlphaFullCPU.py @@ -9,6 +9,8 @@ class DerivAlphaFullCPU(BaseCPU): if not build_env['FULL_SYSTEM']: mem = Param.FunctionalMemory(NULL, "memory") + checker = Param.BaseCPU(NULL, "checker") + cachePorts = Param.Unsigned("Cache Ports") decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") @@ -50,6 +52,8 @@ class DerivAlphaFullCPU(BaseCPU): renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") commitWidth = Param.Unsigned("Commit width") squashWidth = Param.Unsigned("Squash width") + trapLatency = Param.Tick("Trap latency") + fetchTrapLatency = Param.Tick("Fetch trap latency") localPredictorSize = Param.Unsigned("Size of local predictor") localCtrBits = Param.Unsigned("Bits per counter")