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Merge zizzer.eecs.umich.edu:/bk/m5

Browse source 
into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest

--HG--
extra : convert_revision : 64eca6a11aeae236e802f9ca8eb97ca05d394ec7
This commit is contained in:
Nathan Binkert 2004-11-10 18:37:33 -05:00
commit ab8409738e
4 changed files with 18 additions and 20 deletions
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24
arch/alpha/ev5.cc
View file

@ -101,17 +101,17 @@ AlphaISA::initIPRs(RegFile *regs)
} }
template <class XC> template <class CPU>
void void
AlphaISA::processInterrupts(XC *xc) AlphaISA::processInterrupts(CPU *cpu)
{ {
//Check if there are any outstanding interrupts //Check if there are any outstanding interrupts
//Handle the interrupts //Handle the interrupts
int ipl = 0; int ipl = 0;
int summary = 0; int summary = 0;
IntReg *ipr = xc->getIprPtr(); IntReg *ipr = cpu->getIprPtr();
check_interrupts = 0; cpu->checkInterrupts = false;
if (ipr[IPR_ASTRR]) if (ipr[IPR_ASTRR])
panic("asynchronous traps not implemented\n"); panic("asynchronous traps not implemented\n");
@ -127,7 +127,7 @@ AlphaISA::processInterrupts(XC *xc)
} }
} }
uint64_t interrupts = xc->intr_status(); uint64_t interrupts = cpu->intr_status();
if (interrupts) { if (interrupts) {
for (int i = INTLEVEL_EXTERNAL_MIN; for (int i = INTLEVEL_EXTERNAL_MIN;
@ -143,22 +143,22 @@ AlphaISA::processInterrupts(XC *xc)
if (ipl && ipl > ipr[IPR_IPLR]) { if (ipl && ipl > ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary; ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl; ipr[IPR_INTID] = ipl;
xc->trap(Interrupt_Fault); cpu->trap(Interrupt_Fault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary); ipr[IPR_IPLR], ipl, summary);
} }
} }
template <class XC> template <class CPU>
void void
AlphaISA::zeroRegisters(XC *xc) AlphaISA::zeroRegisters(CPU *cpu)
{ {
// Insure ISA semantics // Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the // (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.) // cpu model. Consider changing later.)
xc->xc->setIntReg(ZeroReg, 0); cpu->xc->setIntReg(ZeroReg, 0);
xc->xc->setFloatRegDouble(ZeroReg, 0.0); cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
} }
void void
@ -220,8 +220,6 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
// that's it! (orders of magnitude less painful than x86) // that's it! (orders of magnitude less painful than x86)
} }
bool AlphaISA::check_interrupts = false;
Fault Fault
ExecContext::hwrei() ExecContext::hwrei()
{ {
@ -238,7 +236,7 @@ ExecContext::hwrei()
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(&regs, false); AlphaISA::swap_palshadow(&regs, false);
AlphaISA::check_interrupts = true; cpu->checkInterrupts = true;
} }
// FIXME: XXX check for interrupts? XXX // FIXME: XXX check for interrupts? XXX

7
cpu/base_cpu.cc
View file

@ -53,8 +53,9 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
Counter max_loads_any_thread, Counter max_loads_any_thread,
Counter max_loads_all_threads, Counter max_loads_all_threads,
System *_system, Tick freq) System *_system, Tick freq)
: SimObject(_name), frequency(freq), deferRegistration(_def_reg), : SimObject(_name), frequency(freq), checkInterrupts(true),
number_of_threads(_number_of_threads), system(_system) deferRegistration(_def_reg), number_of_threads(_number_of_threads),
system(_system)
#else #else
BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
Counter max_insts_any_thread, Counter max_insts_any_thread,
@ -219,7 +220,7 @@ BaseCPU::post_interrupt(int int_num, int index)
if (index < 0 || index >= sizeof(uint64_t) * 8) if (index < 0 || index >= sizeof(uint64_t) * 8)
panic("int_num out of bounds\n"); panic("int_num out of bounds\n");
AlphaISA::check_interrupts = 1; checkInterrupts = true;
interrupts[int_num] |= 1 << index; interrupts[int_num] |= 1 << index;
intstatus |= (ULL(1) << int_num); intstatus |= (ULL(1) << int_num);
} }

1
cpu/base_cpu.hh
View file

@ -55,6 +55,7 @@ class BaseCPU : public SimObject
virtual void post_interrupt(int int_num, int index); virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index); virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts(); virtual void clear_interrupts();
bool checkInterrupts;
bool check_interrupt(int int_num) const { bool check_interrupt(int int_num) const {
if (int_num > NumInterruptLevels) if (int_num > NumInterruptLevels)

6
cpu/simple_cpu/simple_cpu.cc
View file

@ -641,13 +641,11 @@ SimpleCPU::tick()
Fault fault = No_Fault; Fault fault = No_Fault;
#ifdef FULL_SYSTEM #ifdef FULL_SYSTEM
if (AlphaISA::check_interrupts && if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
xc->cpu->check_interrupts() &&
!PC_PAL(xc->regs.pc) &&
status() != IcacheMissComplete) { status() != IcacheMissComplete) {
int ipl = 0; int ipl = 0;
int summary = 0; int summary = 0;
AlphaISA::check_interrupts = 0; checkInterrupts = false;
IntReg *ipr = xc->regs.ipr; IntReg *ipr = xc->regs.ipr;
if (xc->regs.ipr[TheISA::IPR_SIRR]) { if (xc->regs.ipr[TheISA::IPR_SIRR]) {