X86: Various fixes to indexing segmentation related registers
--HG-- extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
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6 changed files with 21 additions and 12 deletions
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@ -56,6 +56,7 @@
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*/
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#include "arch/x86/insts/static_inst.hh"
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#include "arch/x86/segmentregs.hh"
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namespace X86ISA
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{
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@ -75,24 +76,27 @@ namespace X86ISA
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{
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switch (segment)
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{
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case 0:
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case SEGMENT_REG_ES:
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ccprintf(os, "ES");
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break;
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case 1:
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case SEGMENT_REG_CS:
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ccprintf(os, "CS");
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break;
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case 2:
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case SEGMENT_REG_SS:
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ccprintf(os, "SS");
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break;
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case 3:
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case SEGMENT_REG_DS:
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ccprintf(os, "DS");
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break;
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case 4:
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case SEGMENT_REG_FS:
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ccprintf(os, "FS");
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break;
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case 5:
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case SEGMENT_REG_GS:
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ccprintf(os, "GS");
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break;
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case SEGMENT_REG_INT:
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ccprintf(os, "INT");
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break;
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default:
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panic("Unrecognized segment %d\n", segment);
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}
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@ -108,7 +108,7 @@ let {{
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# This segment selects an internal address space mapped to MSRs,
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# CPUID info, etc.
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assembler.symbols["intseg"] = "NUM_SEGMENTREGS"
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assembler.symbols["intseg"] = "SEGMENT_REG_INT"
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for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
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assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
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@ -123,7 +123,7 @@ def template MicroLoadExecute {{
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment));
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fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
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if(fault == NoFault)
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{
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@ -150,7 +150,7 @@ def template MicroLoadInitiateAcc {{
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment));
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fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
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return fault;
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}
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@ -197,7 +197,7 @@ def template MicroStoreExecute {{
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if(fault == NoFault)
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{
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fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment));
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fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
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if(fault == NoFault)
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{
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%(op_wb)s;
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@ -224,7 +224,7 @@ def template MicroStoreInitiateAcc {{
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if(fault == NoFault)
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{
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fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment));
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fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
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if(fault == NoFault)
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{
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%(op_wb)s;
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@ -258,6 +258,7 @@ namespace X86ISA
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MISCREG_DS,
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MISCREG_FS,
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MISCREG_GS,
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MISCREG_INT, // This isn't actually used.
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// Hidden segment base field
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MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
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@ -267,6 +268,7 @@ namespace X86ISA
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MISCREG_DS_BASE,
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MISCREG_FS_BASE,
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MISCREG_GS_BASE,
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MISCREG_INT_BASE,
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// Hidden segment limit field
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MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
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@ -276,6 +278,7 @@ namespace X86ISA
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MISCREG_DS_LIMIT,
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MISCREG_FS_LIMIT,
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MISCREG_GS_LIMIT,
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MISCREG_INT_LIMIT, // This isn't actually used.
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// Hidden segment limit attributes
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MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
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@ -285,6 +288,7 @@ namespace X86ISA
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MISCREG_DS_ATTR,
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MISCREG_FS_ATTR,
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MISCREG_GS_ATTR,
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MISCREG_INT_ATTR, // This isn't actually used.
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// System segment selectors
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MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
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@ -68,6 +68,7 @@ namespace X86ISA
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SEGMENT_REG_DS,
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SEGMENT_REG_FS,
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SEGMENT_REG_GS,
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SEGMENT_REG_INT,
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NUM_SEGMENTREGS
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};
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@ -150,7 +150,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
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// If this is true, we're dealing with a request to read an internal
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// value.
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if (seg == NUM_SEGMENTREGS) {
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if (seg == SEGMENT_REG_INT) {
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Addr prefix = vaddr & IntAddrPrefixMask;
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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