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config: Bump DRAM sweep bus speed to match DDR4 config

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This patch bumps the bus clock speed such that the interconnect does
not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2
GByte/s theoretical max.
This commit is contained in:
Andreas Hansson 2014-05-09 18:58:49 -04:00
parent 64806c4c13
commit aa329f4757
1 changed files with 3 additions and 3 deletions
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6
configs/dram/sweep.py
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@ -67,11 +67,11 @@ if args:
# at the moment we stay with the default open-adaptive page policy,
# and address mapping
# start with the system itself, using a multi-layer 1 GHz
# start with the system itself, using a multi-layer 1.5 GHz
# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle)
# which amounts to 12.8 GByte/s per layer and thus per port
# which amounts to 19.2 GByte/s per layer and thus per port
system = System(membus = NoncoherentBus(width = 16))
system.clk_domain = SrcClockDomain(clock = '1GHz',
system.clk_domain = SrcClockDomain(clock = '1.5GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))